llvm-for-llvmta/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
---
name: fpext_v4s64_v4s32
tracksRegLiveness: true
liveins:
- { reg: '$q0' }
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $q0, $x0
; CHECK-LABEL: name: fpext_v4s64_v4s32
; CHECK: liveins: $q0, $x0
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; CHECK: [[FPEXT:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
; CHECK: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT]](<2 x s64>)
; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT1]](<2 x s64>)
; CHECK: G_STORE [[UV2]](s64), [[COPY1]](p0) :: (store 8, align 32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64)
; CHECK: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store 8 + 8)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
; CHECK: G_STORE [[UV4]](s64), [[PTR_ADD1]](p0) :: (store 8 + 16, align 16)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
; CHECK: G_STORE [[UV5]](s64), [[PTR_ADD2]](p0) :: (store 8 + 24)
; CHECK: RET_ReallyLR
%0:_(<4 x s32>) = COPY $q0
%1:_(p0) = COPY $x0
%2:_(<4 x s64>) = G_FPEXT %0(<4 x s32>)
G_STORE %2(<4 x s64>), %1(p0) :: (store 32)
RET_ReallyLR
...