164 lines
4.2 KiB
YAML
164 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define void @test_extload() {
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entry:
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ret void
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}
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define i64 @sext_i32_i64(i32* %ptr) {
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%ld = load i32, i32* %ptr, align 4
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%v = sext i32 %ld to i64
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ret i64 %v
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}
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define i64 @sext_i16_i64(i16* %ptr) {
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%ld = load i16, i16* %ptr, align 2
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%v = sext i16 %ld to i64
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ret i64 %v
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}
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define i64 @sext_i8_i64(i8* %ptr) {
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%ld = load i8, i8* %ptr, align 1
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%v = sext i8 %ld to i64
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ret i64 %v
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}
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define i64 @zext_i32_i64(i32* %ptr) {
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%ld = load i32, i32* %ptr, align 4
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%v = zext i32 %ld to i64
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ret i64 %v
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}
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define i64 @zext_i16_i64(i16* %ptr) {
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%ld = load i16, i16* %ptr, align 2
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%v = zext i16 %ld to i64
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ret i64 %v
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}
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define i64 @zext_i8_i64(i8* %ptr) {
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%ld = load i8, i8* %ptr, align 1
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%v = zext i8 %ld to i64
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ret i64 %v
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}
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...
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---
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name: test_extload
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_extload
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
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; CHECK: $w0 = COPY [[LOAD]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s32) = G_LOAD %0 :: (load 1)
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$w0 = COPY %1
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...
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---
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name: sext_i32_i64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: sext_i32_i64
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
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; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: sext_i16_i64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: sext_i16_i64
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr)
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; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: sext_i8_i64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: sext_i8_i64
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.ptr)
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; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: zext_i32_i64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: zext_i32_i64
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
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; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: zext_i16_i64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: zext_i16_i64
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr)
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; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: zext_i8_i64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: zext_i8_i64
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.ptr)
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; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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