964 lines
26 KiB
YAML
964 lines
26 KiB
YAML
# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
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# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
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--- |
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; ModuleID = 'generic-virtual-registers-type-error.mir'
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @defaultMapping() {
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entry:
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ret void
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}
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define void @defaultMappingVector() {
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entry:
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ret void
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}
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define void @defaultMapping1Repair() {
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entry:
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ret void
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}
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define void @defaultMapping2Repairs() {
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entry:
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ret void
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}
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define void @defaultMappingDefRepair() {
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entry:
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ret void
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}
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define void @phiPropagation(i32* %src, i32* %dst, i1 %cond) {
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entry:
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%srcVal = load i32, i32* %src
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br i1 %cond, label %end, label %then
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then:
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%res = add i32 %srcVal, 36
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br label %end
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end:
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%toStore = phi i32 [ %srcVal, %entry ], [ %res, %then ]
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store i32 %toStore, i32* %dst
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ret void
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}
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define void @defaultMappingUseRepairPhysReg() {
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entry:
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ret void
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}
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define void @defaultMappingDefRepairPhysReg() {
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entry:
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ret void
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}
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define void @greedyMappingOr() {
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entry:
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ret void
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}
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define void @greedyMappingOrWithConstraints() {
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entry:
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ret void
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}
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define void @ignoreTargetSpecificInst() { ret void }
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define void @regBankSelected_property() { ret void }
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define void @bitcast_s32_gpr() { ret void }
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define void @bitcast_s32_fpr() { ret void }
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define void @bitcast_s32_gpr_fpr() { ret void }
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define void @bitcast_s32_fpr_gpr() { ret void }
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define void @bitcast_s64_gpr() { ret void }
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define void @bitcast_s64_fpr() { ret void }
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define void @bitcast_s64_gpr_fpr() { ret void }
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define void @bitcast_s64_fpr_gpr() { ret void }
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define void @bitcast_s128() { ret void }
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define void @copy_s128() { ret void }
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define void @copy_s128_from_load() { ret void }
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define void @copy_fp16() { ret void }
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define i64 @greedyWithChainOfComputation(i64 %arg1, <2 x i32>* %addr) {
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%varg1 = bitcast i64 %arg1 to <2 x i32>
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%varg2 = load <2 x i32>, <2 x i32>* %addr
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%vres = or <2 x i32> %varg1, %varg2
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%res = bitcast <2 x i32> %vres to i64
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ret i64 %res
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}
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define i64 @floatingPointLoad(i64 %arg1, double* %addr) {
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%varg1 = bitcast i64 %arg1 to double
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%varg2 = load double, double* %addr
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%vres = fadd double %varg1, %varg2
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%res = bitcast double %vres to i64
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ret i64 %res
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}
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define void @floatingPointStore(i64 %arg1, double* %addr) {
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%varg1 = bitcast i64 %arg1 to double
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%vres = fadd double %varg1, %varg1
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store double %vres, double* %addr
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ret void
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}
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define void @fp16Ext32() { ret void }
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define void @fp16Ext64() { ret void }
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define void @fp32Ext64() { ret void }
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define half @passFp16(half %p) {
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entry:
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ret half %p
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}
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define half @passFp16ViaAllocas(half %p) {
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entry:
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%p.addr = alloca half, align 2
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store half %p, half* %p.addr, align 2
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%0 = load half, half* %p.addr, align 2
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ret half %0
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}
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...
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---
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# Check that we assign a relevant register bank for %0.
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# Based on the type i32, this should be gpr.
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name: defaultMapping
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: defaultMapping
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; CHECK: %1:gpr(s32) = G_ADD %0
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%0(s32) = COPY $w0
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%1(s32) = G_ADD %0, %0
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...
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---
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# Check that we assign a relevant register bank for %0.
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# Based on the type <2 x i32>, this should be fpr.
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# FPR is used for both floating point and vector registers.
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name: defaultMappingVector
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: $d0
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; CHECK-LABEL: name: defaultMappingVector
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; CHECK: %0:fpr(<2 x s32>) = COPY $d0
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; CHECK: %1:fpr(<2 x s32>) = G_ADD %0
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%0(<2 x s32>) = COPY $d0
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%1(<2 x s32>) = G_ADD %0, %0
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...
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---
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# Check that we repair the assignment for %0.
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# Indeed based on the source of the copy it should live
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# in FPR, but at the use, it should be GPR.
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name: defaultMapping1Repair
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0.entry:
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liveins: $s0, $x0
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; CHECK-LABEL: name: defaultMapping1Repair
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; CHECK: %0:fpr(s32) = COPY $s0
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; CHECK-NEXT: %1:gpr(s32) = COPY $w0
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; CHECK-NEXT: %3:gpr(s32) = COPY %0
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; CHECK-NEXT: %2:gpr(s32) = G_ADD %3, %1
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%0(s32) = COPY $s0
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%1(s32) = COPY $w0
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%2(s32) = G_ADD %0, %1
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...
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# Check that we repair the assignment for %0 differently for both uses.
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name: defaultMapping2Repairs
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: $s0, $x0
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; CHECK-LABEL: name: defaultMapping2Repairs
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; CHECK: %0:fpr(s32) = COPY $s0
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; CHECK-NEXT: %2:gpr(s32) = COPY %0
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; CHECK-NEXT: %3:gpr(s32) = COPY %0
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; CHECK-NEXT: %1:gpr(s32) = G_ADD %2, %3
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%0(s32) = COPY $s0
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%1(s32) = G_ADD %0, %0
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...
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---
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# Check that we repair the definition of %1.
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# %1 is forced to be into FPR, but its definition actually
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# requires that it lives in GPR. Make sure regbankselect
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# fixes that.
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name: defaultMappingDefRepair
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: fpr }
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: defaultMappingDefRepair
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; CHECK: %0:gpr(s32) = COPY $w0
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; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %0
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; CHECK-NEXT: %1:fpr(s32) = COPY %2
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%0(s32) = COPY $w0
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%1(s32) = G_ADD %0, %0
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...
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---
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# Check that we are able to propagate register banks from phis.
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name: phiPropagation
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legalized: true
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tracksRegLiveness: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr64sp, preferred-register: '' }
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# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
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# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr64sp }
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- { id: 2, class: gpr32 }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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body: |
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bb.0.entry:
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successors: %bb.2.end, %bb.1.then
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liveins: $x0, $x1, $w2
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%0 = LDRWui killed $x0, 0 :: (load 4 from %ir.src)
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%5(s32) = COPY %0
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%1(p0) = COPY $x1
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%2 = COPY $w2
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TBNZW killed %2, 0, %bb.2.end
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bb.1.then:
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successors: %bb.2.end
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%3(s32) = G_ADD %5, %5
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bb.2.end:
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%4(s32) = PHI %0, %bb.0.entry, %3, %bb.1.then
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G_STORE killed %4, killed %1 :: (store 4 into %ir.dst)
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RET_ReallyLR
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...
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---
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# Make sure we can repair physical register uses as well.
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name: defaultMappingUseRepairPhysReg
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0.entry:
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liveins: $w0, $s0
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; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
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; CHECK: %0:gpr(s32) = COPY $w0
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; CHECK-NEXT: %1:fpr(s32) = COPY $s0
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; CHECK-NEXT: %3:gpr(s32) = COPY %1
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; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %3
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%0(s32) = COPY $w0
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%1(s32) = COPY $s0
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%2(s32) = G_ADD %0, %1
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...
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---
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# Make sure we can repair physical register defs.
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name: defaultMappingDefRepairPhysReg
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: defaultMappingDefRepairPhysReg
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; CHECK: %0:gpr(s32) = COPY $w0
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; CHECK-NEXT: %1:gpr(s32) = G_ADD %0, %0
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; CHECK-NEXT: $s0 = COPY %1
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%0(s32) = COPY $w0
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%1(s32) = G_ADD %0, %0
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$s0 = COPY %1
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...
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---
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# Check that the greedy mode is able to switch the
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# G_OR instruction from fpr to gpr.
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name: greedyMappingOr
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK: %0:gpr(<2 x s32>) = COPY $x0
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; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1
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; Fast mode tries to reuse the source of the copy for the destination.
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; Now, the default mapping says that %0 and %1 need to be in FPR.
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; The repairing code insert two copies to materialize that.
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; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
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; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
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; The mapping of G_OR is on FPR.
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; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
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; Greedy mode remapped the instruction on the GPR bank.
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; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1
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%0(<2 x s32>) = COPY $x0
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%1(<2 x s32>) = COPY $x1
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%2(<2 x s32>) = G_OR %0, %1
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...
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---
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# Check that the greedy mode is able to switch the
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# G_OR instruction from fpr to gpr, while still honoring
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# %2 constraint.
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name: greedyMappingOrWithConstraints
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legalized: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: fpr }
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: greedyMappingOrWithConstraints
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; CHECK: %0:gpr(<2 x s32>) = COPY $x0
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; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1
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; Fast mode tries to reuse the source of the copy for the destination.
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; Now, the default mapping says that %0 and %1 need to be in FPR.
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; The repairing code insert two copies to materialize that.
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; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
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; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
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; The mapping of G_OR is on FPR.
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; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
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; Greedy mode remapped the instruction on the GPR bank.
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; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1
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; We need to keep %2 into FPR because we do not know anything about it.
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; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3
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%0(<2 x s32>) = COPY $x0
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%1(<2 x s32>) = COPY $x1
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%2(<2 x s32>) = G_OR %0, %1
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...
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---
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# CHECK-LABEL: name: ignoreTargetSpecificInst
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name: ignoreTargetSpecificInst
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legalized: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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body: |
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bb.0:
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liveins: $x0
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; CHECK: %0:gpr64 = COPY $x0
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; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0
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; CHECK-NEXT: $x0 = COPY %1
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0 = COPY $x0
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%1 = ADDXrr %0, %0
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$x0 = COPY %1
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RET_ReallyLR implicit $x0
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...
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---
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# Check that we set the "regBankSelected" property.
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# CHECK-LABEL: name: regBankSelected_property
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# CHECK: legalized: true
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# CHECK: regBankSelected: true
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name: regBankSelected_property
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legalized: true
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regBankSelected: false
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body: |
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bb.0:
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...
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---
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# CHECK-LABEL: name: bitcast_s32_gpr
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name: bitcast_s32_gpr
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legalized: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
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# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '' }
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# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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# CHECK: body:
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# CHECK: %0:gpr(s32) = COPY $w0
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# FAST-NEXT: %1:fpr(<4 x s8>) = G_BITCAST %0
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# GREEDY-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0
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# The greedy check is incorrect and should produce fpr.
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body: |
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bb.0:
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liveins: $w0
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%0(s32) = COPY $w0
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%1(<4 x s8>) = G_BITCAST %0
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...
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---
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# CHECK-LABEL: name: bitcast_s32_fpr
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name: bitcast_s32_fpr
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legalized: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
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# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
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# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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# CHECK: body:
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# CHECK: %0:fpr(<2 x s16>) = COPY $s0
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# FAST: %1:gpr(s32) = G_BITCAST %0
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# GREEDY: %1:fpr(s32) = G_BITCAST %0
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body: |
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bb.0:
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liveins: $s0
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%0(<2 x s16>) = COPY $s0
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%1(s32) = G_BITCAST %0
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...
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---
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# CHECK-LABEL: name: bitcast_s32_gpr_fpr
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name: bitcast_s32_gpr_fpr
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legalized: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
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# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '' }
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# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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# CHECK: body:
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# CHECK: %0:gpr(s32) = COPY $w0
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# FAST: %1:fpr(<2 x s16>) = G_BITCAST %0
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# GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0
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body: |
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bb.0:
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liveins: $w0
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%0(s32) = COPY $w0
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%1(<2 x s16>) = G_BITCAST %0
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...
|
|
|
|
---
|
|
# CHECK-LABEL: name: bitcast_s32_fpr_gpr
|
|
name: bitcast_s32_fpr_gpr
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: body:
|
|
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
|
|
# FAST: %1:gpr(s32) = G_BITCAST %0
|
|
# GREEDY: %1:fpr(s32) = G_BITCAST %0
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0
|
|
|
|
%0(<2 x s16>) = COPY $s0
|
|
%1(s32) = G_BITCAST %0
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: bitcast_s64_gpr
|
|
name: bitcast_s64_gpr
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: body:
|
|
# CHECK: %0:gpr(s64) = COPY $x0
|
|
# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
|
|
# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
%0(s64) = COPY $x0
|
|
%1(<2 x s32>) = G_BITCAST %0
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: bitcast_s64_fpr
|
|
name: bitcast_s64_fpr
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: body:
|
|
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
|
|
# FAST: %1:gpr(s64) = G_BITCAST %0
|
|
# GREEDY: %1:fpr(s64) = G_BITCAST %0
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0
|
|
|
|
%0(<2 x s32>) = COPY $d0
|
|
%1(s64) = G_BITCAST %0
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: bitcast_s64_gpr_fpr
|
|
name: bitcast_s64_gpr_fpr
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: body:
|
|
# CHECK: %0:gpr(s64) = COPY $x0
|
|
# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
|
|
# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
%0(s64) = COPY $x0
|
|
%1(<2 x s32>) = G_BITCAST %0
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: bitcast_s64_fpr_gpr
|
|
name: bitcast_s64_fpr_gpr
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: body:
|
|
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
|
|
# FAST: %1:gpr(s64) = G_BITCAST %0
|
|
# GREEDY: %1:fpr(s64) = G_BITCAST %0
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0
|
|
|
|
%0(<2 x s32>) = COPY $d0
|
|
%1(s64) = G_BITCAST %0
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: bitcast_s128
|
|
name: bitcast_s128
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _}
|
|
- { id: 1, class: _}
|
|
- { id: 2, class: _}
|
|
- { id: 3, class: _}
|
|
# CHECK: %3:fpr(s128) = G_MERGE_VALUES
|
|
# CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)
|
|
body: |
|
|
bb.1:
|
|
liveins: $x0, $x1
|
|
%0(s64) = COPY $x0
|
|
%1(s64) = COPY $x1
|
|
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
|
|
%2(<2 x s64>) = G_BITCAST %3(s128)
|
|
$q0 = COPY %2(<2 x s64>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: copy_s128
|
|
# This test checks that we issue the proper mapping
|
|
# for copy of size > 64.
|
|
# The mapping should be the same as G_BITCAST.
|
|
name: copy_s128
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _}
|
|
- { id: 1, class: _}
|
|
- { id: 2, class: _}
|
|
- { id: 3, class: _}
|
|
- { id: 4, class: _}
|
|
# CHECK: %3:fpr(s128) = G_MERGE_VALUES
|
|
# CHECK: %4:fpr(s128) = COPY %3(s128)
|
|
# CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)
|
|
body: |
|
|
bb.1:
|
|
liveins: $x0, $x1
|
|
%0(s64) = COPY $x0
|
|
%1(s64) = COPY $x1
|
|
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
|
|
%4(s128) = COPY %3(s128)
|
|
%2(<2 x s64>) = G_BITCAST %4(s128)
|
|
$q0 = COPY %2(<2 x s64>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: copy_s128_from_load
|
|
# This test checks that we issue the proper mapping
|
|
# for copy of size > 64 when the input is neither
|
|
# a physcal register nor a generic register.
|
|
# This used to crash when we moved to the statically
|
|
# computed mapping, because we were assuming non-physregs
|
|
# were generic registers and thus have a type, whereas
|
|
# it is not necessarily the case.
|
|
name: copy_s128_from_load
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: fpr128}
|
|
- { id: 1, class: _}
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fpr128, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
|
|
# CHECK: %1:fpr(s128) = COPY %0
|
|
body: |
|
|
bb.1:
|
|
liveins: $x0
|
|
%0 = LDRQui killed $x0, 0
|
|
%1(s128) = COPY %0
|
|
$q0 = COPY %1(s128)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
|
|
---
|
|
# CHECK-LABEL: name: copy_fp16
|
|
# This test checks that we issue the proper mapping
|
|
# for copy of size == 16 when the destination is a fpr
|
|
# physical register and the source a gpr.
|
|
# We used to crash because we thought that mapping couldn't
|
|
# exist in a copy.
|
|
name: copy_fp16
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _}
|
|
- { id: 1, class: _}
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK: %0:gpr(s32) = COPY $w0
|
|
# CHECK-NEXT: %1:gpr(s16) = G_TRUNC %0(s32)
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
%0(s32) = COPY $w0
|
|
%1(s16) = G_TRUNC %0(s32)
|
|
$h0 = COPY %1(s16)
|
|
RET_ReallyLR implicit $h0
|
|
|
|
...
|
|
|
|
|
|
---
|
|
# Make sure the greedy mode is able to take advantage of the
|
|
# alternative mappings of G_LOAD to coalesce the whole chain
|
|
# of computation on GPR.
|
|
# CHECK-LABEL: name: greedyWithChainOfComputation
|
|
name: greedyWithChainOfComputation
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
# No repairing should be necessary for both modes.
|
|
# CHECK: %0:gpr(s64) = COPY $x0
|
|
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
|
|
# FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
|
|
# FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
|
|
# FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3
|
|
# GREEDY-NEXT: %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
|
|
# GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
|
|
# GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3
|
|
# CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
|
|
# CHECK-NEXT: $x0 = COPY %5(s64)
|
|
# CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1
|
|
|
|
%0(s64) = COPY $x0
|
|
%1(p0) = COPY $x1
|
|
%2(<2 x s32>) = G_BITCAST %0(s64)
|
|
%3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
|
|
%4(<2 x s32>) = G_OR %2, %3
|
|
%5(s64) = G_BITCAST %4(<2 x s32>)
|
|
$x0 = COPY %5(s64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
|
|
---
|
|
# Make sure we map what looks like floating point
|
|
# loads to floating point register bank.
|
|
# CHECK-LABEL: name: floatingPointLoad
|
|
name: floatingPointLoad
|
|
legalized: true
|
|
|
|
# CHECK: registers:
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
|
|
# No repairing should be necessary for both modes.
|
|
# CHECK: %0:gpr(s64) = COPY $x0
|
|
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
|
|
# CHECK-NEXT: %2:fpr(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
|
|
# %0 has been mapped to GPR, we need to repair to match FPR.
|
|
# CHECK-NEXT: %4:fpr(s64) = COPY %0
|
|
# CHECK-NEXT: %3:fpr(s64) = G_FADD %4, %2
|
|
# CHECK-NEXT: $x0 = COPY %3(s64)
|
|
# CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1
|
|
|
|
%0(s64) = COPY $x0
|
|
%1(p0) = COPY $x1
|
|
%2(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
|
|
%3(s64) = G_FADD %0, %2
|
|
$x0 = COPY %3(s64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
|
|
---
|
|
# Make sure we map what looks like floating point
|
|
# stores to floating point register bank.
|
|
# CHECK-LABEL: name: floatingPointStore
|
|
name: floatingPointStore
|
|
legalized: true
|
|
|
|
# CHECK: registers:
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
|
|
# CHECK: %0:gpr(s64) = COPY $x0
|
|
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
|
|
# %0 has been mapped to GPR, we need to repair to match FPR.
|
|
# CHECK-NEXT: %3:fpr(s64) = COPY %0
|
|
# CHECK-NEXT: %4:fpr(s64) = COPY %0
|
|
# CHECK-NEXT: %2:fpr(s64) = G_FADD %3, %4
|
|
# CHECK-NEXT: G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
|
|
# CHECK-NEXT: RET_ReallyLR
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1
|
|
|
|
%0(s64) = COPY $x0
|
|
%1(p0) = COPY $x1
|
|
%2(s64) = G_FADD %0, %0
|
|
G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
|
|
RET_ReallyLR
|
|
|
|
...
|
|
|
|
---
|
|
# Make sure we map FPEXT on FPR register bank.
|
|
# CHECK-LABEL: name: fp16Ext32
|
|
name: fp16Ext32
|
|
alignment: 4
|
|
legalized: true
|
|
# CHECK: registers:
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
# CHECK: %1:gpr(s32) = COPY $w0
|
|
# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
|
|
# %0 has been mapped to GPR, we need to repair to match FPR.
|
|
# CHECK-NEXT: %3:fpr(s16) = COPY %0
|
|
# CHECK-NEXT: %2:fpr(s32) = G_FPEXT %3
|
|
# CHECK-NEXT: $s0 = COPY %2
|
|
# CHECK-NEXT: RET_ReallyLR
|
|
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
%1(s32) = COPY $w0
|
|
%0(s16) = G_TRUNC %1(s32)
|
|
%2(s32) = G_FPEXT %0(s16)
|
|
$s0 = COPY %2(s32)
|
|
RET_ReallyLR implicit $s0
|
|
|
|
...
|
|
|
|
---
|
|
# Make sure we map FPEXT on FPR register bank.
|
|
# CHECK-LABEL: name: fp16Ext64
|
|
name: fp16Ext64
|
|
alignment: 4
|
|
legalized: true
|
|
# CHECK: registers:
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
# CHECK: %1:gpr(s32) = COPY $w0
|
|
# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
|
|
# %0 has been mapped to GPR, we need to repair to match FPR.
|
|
# CHECK-NEXT: %3:fpr(s16) = COPY %0
|
|
# CHECK-NEXT: %2:fpr(s64) = G_FPEXT %3
|
|
# CHECK-NEXT: $d0 = COPY %2
|
|
# CHECK-NEXT: RET_ReallyLR
|
|
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
%1(s32) = COPY $w0
|
|
%0(s16) = G_TRUNC %1(s32)
|
|
%2(s64) = G_FPEXT %0(s16)
|
|
$d0 = COPY %2(s64)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
|
|
---
|
|
# Make sure we map FPEXT on FPR register bank.
|
|
# CHECK-LABEL: name: fp32Ext64
|
|
name: fp32Ext64
|
|
alignment: 4
|
|
legalized: true
|
|
# CHECK: registers:
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: %0:gpr(s32) = COPY $w0
|
|
# %0 has been mapped to GPR, we need to repair to match FPR.
|
|
# CHECK-NEXT: %2:fpr(s32) = COPY %0
|
|
# CHECK-NEXT: %1:fpr(s64) = G_FPEXT %2
|
|
# CHECK-NEXT: $d0 = COPY %1
|
|
# CHECK-NEXT: RET_ReallyLR
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
%0(s32) = COPY $w0
|
|
%1(s64) = G_FPEXT %0(s32)
|
|
$d0 = COPY %1(s64)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
|
|
---
|
|
# Make sure we map FP16 ABI on FPR register bank.
|
|
# CHECK-LABEL: name: passFp16
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
|
|
# CHECK: %0:fpr(s16) = COPY $h0
|
|
# CHECK-NEXT: $h0 = COPY %0(s16)
|
|
name: passFp16
|
|
alignment: 4
|
|
legalized: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $h0
|
|
|
|
%0(s16) = COPY $h0
|
|
$h0 = COPY %0(s16)
|
|
RET_ReallyLR implicit $h0
|
|
|
|
...
|
|
---
|
|
# Make sure we properly detect fp types through copies.
|
|
# In that example, the copy comes from an ABI lowering of a fp type.
|
|
# CHECK-LABEL: name: passFp16ViaAllocas
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fpr, preferred-register: '' }
|
|
#
|
|
# CHECK: %0:fpr(s16) = COPY $h0
|
|
# CHECK-NEXT: %1:gpr(p0) = G_FRAME_INDEX %stack.0.p.addr
|
|
# If we didn't look through the copy for %0, the default mapping
|
|
# would have been on GPR and we would have to insert a copy to move
|
|
# the value away from FPR (h0).
|
|
# CHECK-NEXT: G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr)
|
|
# If we didn't look through the copy for %2, the default mapping
|
|
# would have been on GPR and we would have to insert a copy to move
|
|
# the value to FPR (h0).
|
|
# CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
|
|
# CHECK-NEXT: $h0 = COPY %2(s16)
|
|
name: passFp16ViaAllocas
|
|
alignment: 4
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
frameInfo:
|
|
maxAlignment: 2
|
|
stack:
|
|
- { id: 0, name: p.addr, size: 2, alignment: 2, stack-id: default }
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $h0
|
|
|
|
%0(s16) = COPY $h0
|
|
%1(p0) = G_FRAME_INDEX %stack.0.p.addr
|
|
G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr)
|
|
%2(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
|
|
$h0 = COPY %2(s16)
|
|
RET_ReallyLR implicit $h0
|
|
|
|
...
|