283 lines
7.9 KiB
TableGen
283 lines
7.9 KiB
TableGen
//===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// SX-Aurora uses little endian, but instructions are encoded little bit
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// different manner. Therefore, we need to tranlate the address of each
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// bitfield described in ISA documentation like below.
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//
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// ISA | InstrFormats.td
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// ---------------------------
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// 0-7 => 63-56
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// 8 => 55
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// 32-63 => 31-0
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//===----------------------------------------------------------------------===//
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// Instruction Format
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//===----------------------------------------------------------------------===//
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class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<64> Inst;
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let Namespace = "VE";
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let Size = 8;
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bits<8> op;
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let Inst{63-56} = op;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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bits<1> VE_Vector = 0;
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bits<1> VE_VLInUse = 0;
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bits<3> VE_VLIndex = 0;
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bits<1> VE_VLWithMask = 0;
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/// These fields correspond to the fields in VEInstrInfo.h. Any changes to
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/// these must be reflected there! See comments there for what these are.
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///
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/// VLIndex is the index of VL register in MI's operands. The HW instruction
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/// doesn't have that field, but we add is in MI for the ease of optimization.
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/// For example, the index of VL of (VST $sy, $sz, $sx, $vl) is 3 (beginning
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/// from 0), and the index of VL of (VST $sy, $sz, $sx, $vm, $vl) is 4. We
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/// define vector instructions hierarchically, so use VE_VLIndex which is
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/// defined by the type of instruction and VE_VLWithMask which is defined
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/// whether the insturction use mask or not.
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let TSFlags{0} = VE_Vector;
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let TSFlags{1} = VE_VLInUse;
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let TSFlags{4-2} = !add(VE_VLIndex, VE_VLWithMask);
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let DecoderNamespace = "VE";
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field bits<64> SoftFail = 0;
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}
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//-----------------------------------------------------------------------------
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// Section 5.1 RM Type
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//
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// RM type has sx, sy, sz, and imm32.
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// The effective address is generated by sz + sy + imm32.
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//-----------------------------------------------------------------------------
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class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<7> sx;
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bits<1> cy = 1;
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bits<7> sz; // defines sz prior to sy to assign from sz
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bits<7> sy;
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bits<1> cz = 1;
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bits<32> imm32;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54-48} = sx;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-0} = imm32;
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}
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//-----------------------------------------------------------------------------
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// Section 5.2 RRM Type
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//
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// RRM type is identical to RM, but the effective address is generated
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// by sz + imm32. The sy field is used by other purposes.
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//-----------------------------------------------------------------------------
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class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
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list<dag> pattern = []>
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: RM<opVal, outs, ins, asmstr, pattern>;
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// RRMHM type is to load/store host memory
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// It is similar to RRM and not use sy.
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class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
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list<dag> pattern = []>
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: RRM<opVal, outs, ins, asmstr, pattern> {
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bits<2> ry = 0;
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let cy = 0;
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let sy{6-2} = 0;
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let sy{1-0} = ry;
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}
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//-----------------------------------------------------------------------------
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// Section 5.3 CF Type
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//
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// CF type is used for control flow.
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//-----------------------------------------------------------------------------
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class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<1> cx2 = 0;
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bits<2> bpf = 0;
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bits<4> cf;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 1;
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bits<7> sz;
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bits<32> imm32;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54} = cx2;
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let Inst{53-52} = bpf;
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let Inst{51-48} = cf;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-0} = imm32;
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}
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//-----------------------------------------------------------------------------
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// Section 5.4 RR Type
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//
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// RR type is for generic arithmetic instructions.
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//-----------------------------------------------------------------------------
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class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<7> sx;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 1;
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bits<7> sz; // m field places at the top sz field
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bits<8> vx = 0;
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bits<8> vz = 0;
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bits<1> cw = 0;
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bits<1> cw2 = 0;
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bits<4> cfw = 0;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54-48} = sx;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-24} = vx;
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let Inst{23-16} = 0;
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let Inst{15-8} = vz;
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let Inst{7} = cw;
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let Inst{6} = cw2;
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let Inst{5-4} = 0;
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let Inst{3-0} = cfw;
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}
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// RRFENCE type is special RR type for a FENCE instruction.
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class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,
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list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> avo = 0;
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bits<1> lf = 0;
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bits<1> sf = 0;
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bits<1> c2 = 0;
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bits<1> c1 = 0;
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bits<1> c0 = 0;
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let op = opVal;
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let Inst{55} = avo;
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let Inst{54-50} = 0;
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let Inst{49} = lf;
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let Inst{48} = sf;
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let Inst{47-43} = 0;
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let Inst{42} = c2;
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let Inst{41} = c1;
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let Inst{40} = c0;
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let Inst{39-0} = 0;
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}
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//-----------------------------------------------------------------------------
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// Section 5.5 RW Type
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Section 5.6 RVM Type
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//
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// RVM type is for vector transfer instructions.
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//-----------------------------------------------------------------------------
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class RVM<bits<8>opVal, dag outs, dag ins, string asmstr,
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list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<1> vc = 0;
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bits<1> cs = 0;
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bits<4> m = 0;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 1;
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bits<7> sz;
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bits<8> vx;
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bits<8> vy = 0;
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bits<7> sw = 0;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54} = vc;
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let Inst{53} = cs;
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let Inst{52} = 0;
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let Inst{51-48} = m;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-24} = vx;
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let Inst{23-16} = vy;
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let Inst{15-8} = 0;
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let Inst{7} = 0;
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let Inst{6-0} = sw;
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let VE_Vector = 1;
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}
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//-----------------------------------------------------------------------------
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// Section 5.7 RV Type
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//
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// RV type is for vector instructions.
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//-----------------------------------------------------------------------------
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class RV<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<1> cx2 = 0;
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bits<1> cs = 0;
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bits<1> cs2 = 0;
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bits<4> m = 0;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 0;
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bits<7> sz = 0;
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bits<8> vx = 0;
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bits<8> vy = 0;
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bits<8> vz = 0;
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bits<8> vw = 0;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54} = cx2;
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let Inst{53} = cs;
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let Inst{52} = cs2;
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let Inst{51-48} = m;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-24} = vx;
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let Inst{23-16} = vy;
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let Inst{15-8} = vz;
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let Inst{7-0} = vw;
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let VE_Vector = 1;
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}
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// Pseudo instructions.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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