423 lines
16 KiB
C++
423 lines
16 KiB
C++
//===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZRegisterInfo.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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using namespace llvm;
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#define GET_REGINFO_TARGET_DESC
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#include "SystemZGenRegisterInfo.inc"
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SystemZRegisterInfo::SystemZRegisterInfo()
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: SystemZGenRegisterInfo(SystemZ::R14D) {}
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// Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
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// somehow belongs in it. Otherwise, return GRX32.
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static const TargetRegisterClass *getRC32(MachineOperand &MO,
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const VirtRegMap *VRM,
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const MachineRegisterInfo *MRI) {
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const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
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if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
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MO.getSubReg() == SystemZ::subreg_l32 ||
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MO.getSubReg() == SystemZ::subreg_hl32)
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return &SystemZ::GR32BitRegClass;
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if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
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MO.getSubReg() == SystemZ::subreg_h32 ||
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MO.getSubReg() == SystemZ::subreg_hh32)
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return &SystemZ::GRH32BitRegClass;
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if (VRM && VRM->hasPhys(MO.getReg())) {
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Register PhysReg = VRM->getPhys(MO.getReg());
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if (SystemZ::GR32BitRegClass.contains(PhysReg))
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return &SystemZ::GR32BitRegClass;
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assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
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"Phys reg not in GR32 or GRH32?");
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return &SystemZ::GRH32BitRegClass;
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}
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assert (RC == &SystemZ::GRX32BitRegClass);
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return RC;
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}
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// Pass the registers of RC as hints while making sure that if any of these
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// registers are copy hints (and therefore already in Hints), hint them
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// first.
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static void addHints(ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const TargetRegisterClass *RC,
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const MachineRegisterInfo *MRI) {
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SmallSet<unsigned, 4> CopyHints;
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CopyHints.insert(Hints.begin(), Hints.end());
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Hints.clear();
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for (MCPhysReg Reg : Order)
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if (CopyHints.count(Reg) &&
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RC->contains(Reg) && !MRI->isReserved(Reg))
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Hints.push_back(Reg);
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for (MCPhysReg Reg : Order)
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if (!CopyHints.count(Reg) &&
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RC->contains(Reg) && !MRI->isReserved(Reg))
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Hints.push_back(Reg);
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}
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bool SystemZRegisterInfo::getRegAllocationHints(
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Register VirtReg, ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
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const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
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const MachineRegisterInfo *MRI = &MF.getRegInfo();
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const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
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const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
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bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
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VirtReg, Order, Hints, MF, VRM, Matrix);
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if (VRM != nullptr) {
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// Add any two address hints after any copy hints.
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SmallSet<unsigned, 4> TwoAddrHints;
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for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
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if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
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const MachineOperand *VRRegMO = nullptr;
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const MachineOperand *OtherMO = nullptr;
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const MachineOperand *CommuMO = nullptr;
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if (VirtReg == Use.getOperand(0).getReg()) {
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VRRegMO = &Use.getOperand(0);
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OtherMO = &Use.getOperand(1);
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if (Use.isCommutable())
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CommuMO = &Use.getOperand(2);
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} else if (VirtReg == Use.getOperand(1).getReg()) {
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VRRegMO = &Use.getOperand(1);
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OtherMO = &Use.getOperand(0);
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} else if (VirtReg == Use.getOperand(2).getReg() &&
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Use.isCommutable()) {
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VRRegMO = &Use.getOperand(2);
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OtherMO = &Use.getOperand(0);
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} else
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continue;
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auto tryAddHint = [&](const MachineOperand *MO) -> void {
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Register Reg = MO->getReg();
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Register PhysReg = Register::isPhysicalRegister(Reg)
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? Reg
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: Register(VRM->getPhys(Reg));
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if (PhysReg) {
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if (MO->getSubReg())
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PhysReg = getSubReg(PhysReg, MO->getSubReg());
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if (VRRegMO->getSubReg())
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PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
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MRI->getRegClass(VirtReg));
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if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
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TwoAddrHints.insert(PhysReg);
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}
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};
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tryAddHint(OtherMO);
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if (CommuMO)
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tryAddHint(CommuMO);
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}
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for (MCPhysReg OrderReg : Order)
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if (TwoAddrHints.count(OrderReg))
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Hints.push_back(OrderReg);
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}
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if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
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SmallVector<Register, 8> Worklist;
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SmallSet<Register, 4> DoneRegs;
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Worklist.push_back(VirtReg);
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while (Worklist.size()) {
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Register Reg = Worklist.pop_back_val();
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if (!DoneRegs.insert(Reg).second)
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continue;
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for (auto &Use : MRI->reg_instructions(Reg)) {
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// For LOCRMux, see if the other operand is already a high or low
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// register, and in that case give the corresponding hints for
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// VirtReg. LOCR instructions need both operands in either high or
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// low parts. Same handling for SELRMux.
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if (Use.getOpcode() == SystemZ::LOCRMux ||
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Use.getOpcode() == SystemZ::SELRMux) {
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MachineOperand &TrueMO = Use.getOperand(1);
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MachineOperand &FalseMO = Use.getOperand(2);
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const TargetRegisterClass *RC =
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TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
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getRC32(TrueMO, VRM, MRI));
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if (Use.getOpcode() == SystemZ::SELRMux)
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RC = TRI->getCommonSubClass(RC,
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getRC32(Use.getOperand(0), VRM, MRI));
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if (RC && RC != &SystemZ::GRX32BitRegClass) {
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addHints(Order, Hints, RC, MRI);
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// Return true to make these hints the only regs available to
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// RA. This may mean extra spilling but since the alternative is
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// a jump sequence expansion of the LOCRMux, it is preferred.
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return true;
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}
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// Add the other operand of the LOCRMux to the worklist.
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Register OtherReg =
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(TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
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if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
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Worklist.push_back(OtherReg);
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} // end LOCRMux
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else if (Use.getOpcode() == SystemZ::CHIMux ||
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Use.getOpcode() == SystemZ::CFIMux) {
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if (Use.getOperand(1).getImm() == 0) {
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bool OnlyLMuxes = true;
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for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
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if (DefMI.getOpcode() != SystemZ::LMux)
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OnlyLMuxes = false;
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if (OnlyLMuxes) {
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addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
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// Return false to make these hints preferred but not obligatory.
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return false;
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}
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}
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} // end CHIMux / CFIMux
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}
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}
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}
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return BaseImplRetVal;
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}
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const MCPhysReg *
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SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
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if (MF->getFunction().getCallingConv() == CallingConv::GHC)
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return CSR_SystemZ_NoRegs_SaveList;
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if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
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return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
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: CSR_SystemZ_AllRegs_SaveList;
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if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
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MF->getFunction().getAttributes().hasAttrSomewhere(
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Attribute::SwiftError))
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return CSR_SystemZ_SwiftError_SaveList;
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return CSR_SystemZ_SaveList;
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}
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const uint32_t *
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SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
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if (CC == CallingConv::GHC)
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return CSR_SystemZ_NoRegs_RegMask;
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if (CC == CallingConv::AnyReg)
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return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
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: CSR_SystemZ_AllRegs_RegMask;
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if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
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MF.getFunction().getAttributes().hasAttrSomewhere(
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Attribute::SwiftError))
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return CSR_SystemZ_SwiftError_RegMask;
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return CSR_SystemZ_RegMask;
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}
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BitVector
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SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const SystemZFrameLowering *TFI = getFrameLowering(MF);
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if (TFI->hasFP(MF)) {
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// R11D is the frame pointer. Reserve all aliases.
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11L);
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Reserved.set(SystemZ::R11H);
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Reserved.set(SystemZ::R10Q);
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}
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// R15D is the stack pointer. Reserve all aliases.
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R15L);
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Reserved.set(SystemZ::R15H);
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Reserved.set(SystemZ::R14Q);
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// A0 and A1 hold the thread pointer.
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Reserved.set(SystemZ::A0);
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Reserved.set(SystemZ::A1);
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// FPC is the floating-point control register.
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Reserved.set(SystemZ::FPC);
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return Reserved;
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}
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void
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SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
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MachineBasicBlock &MBB = *MI->getParent();
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MachineFunction &MF = *MBB.getParent();
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auto *TII =
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static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const SystemZFrameLowering *TFI = getFrameLowering(MF);
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DebugLoc DL = MI->getDebugLoc();
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// Decompose the frame index into a base and offset.
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int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
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Register BasePtr;
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int64_t Offset =
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(TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed() +
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MI->getOperand(FIOperandNum + 1).getImm());
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// Special handling of dbg_value instructions.
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if (MI->isDebugValue()) {
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
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MI->getDebugOffset().ChangeToImmediate(Offset);
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return;
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}
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// See if the offset is in range, or if an equivalent instruction that
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// accepts the offset exists.
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unsigned Opcode = MI->getOpcode();
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unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
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if (OpcodeForOffset) {
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if (OpcodeForOffset == SystemZ::LE &&
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MF.getSubtarget<SystemZSubtarget>().hasVector()) {
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// If LE is ok for offset, use LDE instead on z13.
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OpcodeForOffset = SystemZ::LDE32;
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}
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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}
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else {
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// Create an anchor point that is in range. Start at 0xffff so that
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// can use LLILH to load the immediate.
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int64_t OldOffset = Offset;
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int64_t Mask = 0xffff;
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do {
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Offset = OldOffset & Mask;
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OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
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Mask >>= 1;
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assert(Mask && "One offset must be OK");
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} while (!OpcodeForOffset);
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Register ScratchReg =
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MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
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int64_t HighOffset = OldOffset - Offset;
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if (MI->getDesc().TSFlags & SystemZII::HasIndex
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&& MI->getOperand(FIOperandNum + 2).getReg() == 0) {
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// Load the offset into the scratch register and use it as an index.
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// The scratch register then dies here.
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TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
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false, false, true);
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} else {
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// Load the anchor address into a scratch register.
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unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
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if (LAOpcode)
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BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
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.addReg(BasePtr).addImm(HighOffset).addReg(0);
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else {
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// Load the high offset into the scratch register and use it as
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// an index.
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TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
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BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)
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.addReg(BasePtr, RegState::Kill).addImm(0).addReg(ScratchReg);
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}
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// Use the scratch register as the base. It then dies here.
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MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
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false, false, true);
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}
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}
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MI->setDesc(TII->get(OpcodeForOffset));
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MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC,
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LiveIntervals &LIS) const {
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assert (MI->isCopy() && "Only expecting COPY instructions");
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// Coalesce anything which is not a COPY involving a subreg to/from GR128.
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if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
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(getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
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return true;
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// Allow coalescing of a GR128 subreg COPY only if the live ranges are small
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// and local to one MBB with not too much interferring registers. Otherwise
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// regalloc may run out of registers.
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unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
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Register GR128Reg = MI->getOperand(WideOpNo).getReg();
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Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
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LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
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LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
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// Check that the two virtual registers are local to MBB.
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MachineBasicBlock *MBB = MI->getParent();
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MachineInstr *FirstMI_GR128 =
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LIS.getInstructionFromIndex(IntGR128.beginIndex());
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MachineInstr *FirstMI_GRNar =
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LIS.getInstructionFromIndex(IntGRNar.beginIndex());
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MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
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MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
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if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
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(!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
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(!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
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(!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
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return false;
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MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
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if (WideOpNo == 1) {
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MII = FirstMI_GR128;
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MEE = LastMI_GRNar;
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} else {
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MII = FirstMI_GRNar;
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MEE = LastMI_GR128;
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}
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// Check if coalescing seems safe by finding the set of clobbered physreg
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// pairs in the region.
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BitVector PhysClobbered(getNumRegs());
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MEE++;
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for (; MII != MEE; ++MII) {
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for (const MachineOperand &MO : MII->operands())
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if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
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for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
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SI.isValid(); ++SI)
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if (NewRC->contains(*SI)) {
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PhysClobbered.set(*SI);
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break;
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}
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}
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}
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// Demand an arbitrary margin of free regs.
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unsigned const DemandedFreeGR128 = 3;
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if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
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return false;
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return true;
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}
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Register
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SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const SystemZFrameLowering *TFI = getFrameLowering(MF);
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return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
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}
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const TargetRegisterClass *
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SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &SystemZ::CCRRegClass)
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return &SystemZ::GR32BitRegClass;
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return RC;
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}
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