641 lines
33 KiB
TableGen
641 lines
33 KiB
TableGen
//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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//
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//===----------------------------------------------------------------------===//
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// CPU Directives //
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//===----------------------------------------------------------------------===//
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def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
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def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
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def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
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def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
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def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
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def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
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def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
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def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
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def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
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def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
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def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
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def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
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def DirectiveE500 : SubtargetFeature<"", "CPUDirective",
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"PPC::DIR_E500", "">;
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def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
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"PPC::DIR_E500mc", "">;
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def DirectiveE5500 : SubtargetFeature<"", "CPUDirective",
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"PPC::DIR_E5500", "">;
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def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
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def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
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def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
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def DirectivePwr5x
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: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
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def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
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def DirectivePwr6x
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: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
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def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
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def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
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def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
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def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
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def DirectivePwrFuture
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: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
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def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
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"Enable 64-bit instructions">;
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def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
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def FeatureModernAIXAs
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: SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
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"AIX system assembler is modern enough to support new mnes">;
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def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
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"Enable floating-point instructions">;
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
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"Enable 64-bit registers usage for ppc32 [beta]">;
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def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
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"Use condition-register bits individually">;
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def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",
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"Enable classic FPU instructions",
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[FeatureHardFloat]>;
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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"Enable Altivec instructions",
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[FeatureFPU]>;
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def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
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"Enable SPE instructions",
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[FeatureHardFloat]>;
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def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
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"Enable Embedded Floating-Point APU 2 instructions",
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[FeatureSPE]>;
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def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
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"Enable the MFOCRF instruction">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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"Enable the fsqrt instruction",
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[FeatureFPU]>;
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def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
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"Enable the fcpsgn instruction",
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[FeatureFPU]>;
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def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
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"Enable the fre instruction",
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[FeatureFPU]>;
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def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
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"Enable the fres instruction",
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[FeatureFPU]>;
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def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
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"Enable the frsqrte instruction",
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[FeatureFPU]>;
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def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
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"Enable the frsqrtes instruction",
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[FeatureFPU]>;
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def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
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"Assume higher precision reciprocal estimates">;
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction",
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[FeatureFPU]>;
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def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
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"Enable the lfiwax instruction",
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[FeatureFPU]>;
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def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
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"Enable the fri[mnpz] instructions",
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[FeatureFPU]>;
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def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
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"Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
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[FeatureFPU]>;
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def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
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"Enable the bpermd instruction">;
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def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",
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"Enable extended divide instructions">;
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def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
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"Enable the ldbrx instruction">;
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def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
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"Enable the cmpb instruction">;
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def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
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"Enable icbt instruction">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions",
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[FeatureICBT]>;
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def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
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"Has only the msync instruction instead of sync",
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[FeatureBookE]>;
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def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
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"Enable E500/E500mc instructions">;
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def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
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"Enable secure plt mode">;
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def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
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"Enable PPC 4xx instructions">;
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def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
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"Enable PPC 6xx instructions">;
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def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
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"Enable VSX instructions",
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[FeatureAltivec]>;
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def FeatureTwoConstNR :
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SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
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"Requires two constant Newton-Raphson computation">;
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def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
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"Enable POWER8 Altivec instructions",
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[FeatureAltivec]>;
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def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
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"Enable POWER8 Crypto instructions",
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[FeatureP8Altivec]>;
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def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
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"Enable POWER8 vector instructions",
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[FeatureVSX, FeatureP8Altivec]>;
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def FeatureDirectMove :
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SubtargetFeature<"direct-move", "HasDirectMove", "true",
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"Enable Power8 direct move instructions",
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[FeatureVSX]>;
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def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
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"HasPartwordAtomics", "true",
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"Enable l[bh]arx and st[bh]cx.">;
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def FeatureInvariantFunctionDescriptors :
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SubtargetFeature<"invariant-function-descriptors",
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"HasInvariantFunctionDescriptors", "true",
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"Assume function descriptors are invariant">;
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def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
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"Always use indirect calls">;
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def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
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"Enable Hardware Transactional Memory instructions">;
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def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true",
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"Implement mftb using the mfspr instruction">;
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def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
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"Target supports instruction fusion">;
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def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
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"HasAddiLoadFusion", "true",
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"Power8 Addi-Load fusion",
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[FeatureFusion]>;
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def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
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"HasAddisLoadFusion", "true",
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"Power8 Addis-Load fusion",
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[FeatureFusion]>;
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def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
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"Target supports store clustering",
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[FeatureFusion]>;
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def FeatureUnalignedFloats :
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SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
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"true", "CPU does not trap on unaligned FP access">;
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def FeaturePPCPreRASched:
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SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
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"Use PowerPC pre-RA scheduling strategy">;
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def FeaturePPCPostRASched:
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SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
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"Use PowerPC post-RA scheduling strategy">;
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def FeatureFloat128 :
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SubtargetFeature<"float128", "HasFloat128", "true",
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"Enable the __float128 data type for IEEE-754R Binary128.",
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[FeatureVSX]>;
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def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD",
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"POPCNTD_Fast",
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"Enable the popcnt[dw] instructions">;
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// Note that for the a2 processor models we should not use popcnt[dw] by
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// default. These processors do support the instructions, but they're
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// microcoded, and the software emulation is about twice as fast.
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def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
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"POPCNTD_Slow",
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"Has slow popcnt[dw] instructions">;
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def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
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"Treat vector data stream cache control instructions as deprecated">;
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def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
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"true",
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"Enable instructions in ISA 3.0.">;
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def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
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"true",
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"Enable instructions in ISA 3.1.",
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[FeatureISA3_0]>;
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def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
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"Enable POWER9 Altivec instructions",
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[FeatureISA3_0, FeatureP8Altivec]>;
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def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
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"Enable POWER9 vector instructions",
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[FeatureISA3_0, FeatureP8Vector,
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FeatureP9Altivec]>;
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def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector",
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"true",
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"Enable POWER10 vector instructions",
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[FeatureISA3_1, FeatureP9Vector]>;
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// A separate feature for this even though it is equivalent to P9Vector
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// because this is a feature of the implementation rather than the architecture
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// and may go away with future CPU's.
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def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
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"VectorsUseTwoUnits",
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"true",
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"Vectors use two units">;
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def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
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"true",
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"Enable prefixed instructions",
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[FeatureISA3_0, FeatureP8Vector,
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FeatureP9Altivec]>;
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def FeaturePCRelativeMemops :
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SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
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"Enable PC relative Memory Ops",
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[FeatureISA3_0, FeaturePrefixInstrs]>;
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def FeaturePairedVectorMemops:
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SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
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"32Byte load and store instructions",
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[FeatureISA3_0]>;
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def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
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"Enable MMA instructions",
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[FeatureP8Vector, FeatureP9Altivec,
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FeaturePairedVectorMemops]>;
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def FeaturePredictableSelectIsExpensive :
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SubtargetFeature<"predictable-select-expensive",
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"PredictableSelectIsExpensive",
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"true",
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"Prefer likely predicted branches over selects">;
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// Since new processors generally contain a superset of features of those that
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// came before them, the idea is to make implementations of new processors
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// less error prone and easier to read.
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// Namely:
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// list<SubtargetFeature> P8InheritableFeatures = ...
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// list<SubtargetFeature> FutureProcessorAddtionalFeatures =
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// [ features that Power8 does not support but inheritable ]
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// list<SubtargetFeature> FutureProcessorSpecificFeatures =
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// [ features that Power8 does not support and not inheritable ]
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// list<SubtargetFeature> FutureProcessorInheritableFeatures =
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// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
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// list<SubtargetFeature> FutureProcessorFeatures =
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// !listconcat(FutureProcessorInheritableFeatures,
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// FutureProcessorSpecificFeatures)
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// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
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// well as providing a single point of definition if the feature set will be
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// used elsewhere.
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def ProcessorFeatures {
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// Power7
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list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
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FeatureAltivec,
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FeatureVSX,
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FeatureMFOCRF,
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FeatureFCPSGN,
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FeatureFSqrt,
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FeatureFRE,
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FeatureFRES,
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FeatureFRSQRTE,
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FeatureFRSQRTES,
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FeatureRecipPrec,
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FeatureSTFIWX,
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FeatureLFIWAX,
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FeatureFPRND,
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FeatureFPCVT,
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FeatureISEL,
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FeaturePOPCNTD,
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FeatureCMPB,
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FeatureLDBRX,
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Feature64Bit,
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/* Feature64BitRegs, */
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FeatureBPERMD,
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FeatureExtDiv,
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FeatureMFTB,
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DeprecatedDST,
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FeatureTwoConstNR,
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FeatureUnalignedFloats];
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list<SubtargetFeature> P7SpecificFeatures = [];
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list<SubtargetFeature> P7Features =
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!listconcat(P7InheritableFeatures, P7SpecificFeatures);
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// Power8
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list<SubtargetFeature> P8AdditionalFeatures =
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[DirectivePwr8,
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FeatureP8Altivec,
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FeatureP8Vector,
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FeatureP8Crypto,
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FeatureHTM,
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FeatureDirectMove,
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FeatureICBT,
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FeaturePartwordAtomic,
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FeaturePredictableSelectIsExpensive
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];
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list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
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FeatureAddisLoadFusion];
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list<SubtargetFeature> P8InheritableFeatures =
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!listconcat(P7InheritableFeatures, P8AdditionalFeatures);
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list<SubtargetFeature> P8Features =
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!listconcat(P8InheritableFeatures, P8SpecificFeatures);
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// Power9
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list<SubtargetFeature> P9AdditionalFeatures =
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[DirectivePwr9,
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FeatureP9Altivec,
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FeatureP9Vector,
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FeaturePPCPreRASched,
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FeaturePPCPostRASched,
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FeatureISA3_0,
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FeaturePredictableSelectIsExpensive
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];
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// Some features are unique to Power9 and there is no reason to assume
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// they will be part of any future CPUs. One example is the narrower
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// dispatch for vector operations than scalar ones. For the time being,
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// this list also includes scheduling-related features since we do not have
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// enough info to create custom scheduling strategies for future CPUs.
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list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
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list<SubtargetFeature> P9InheritableFeatures =
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!listconcat(P8InheritableFeatures, P9AdditionalFeatures);
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list<SubtargetFeature> P9Features =
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!listconcat(P9InheritableFeatures, P9SpecificFeatures);
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// Power10
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// For P10 CPU we assume that all of the existing features from Power9
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// still exist with the exception of those we know are Power9 specific.
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list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion];
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list<SubtargetFeature> P10AdditionalFeatures =
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!listconcat(FusionFeatures, [
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DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
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FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
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FeaturePairedVectorMemops]);
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list<SubtargetFeature> P10SpecificFeatures = [];
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list<SubtargetFeature> P10InheritableFeatures =
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!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
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list<SubtargetFeature> P10Features =
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!listconcat(P10InheritableFeatures, P10SpecificFeatures);
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// Future
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// For future CPU we assume that all of the existing features from Power10
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// still exist with the exception of those we know are Power10 specific.
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list<SubtargetFeature> FutureAdditionalFeatures = [];
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list<SubtargetFeature> FutureSpecificFeatures = [];
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list<SubtargetFeature> FutureInheritableFeatures =
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!listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
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list<SubtargetFeature> FutureFeatures =
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!listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
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}
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// Note: Future features to add when support is extended to more
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// recent ISA levels:
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//
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// DFP p6, p6x, p7 decimal floating-point instructions
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// POPCNTB p5 through p7 popcntb and related instructions
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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// RecFormRel - Filter class used to relate non-record-form instructions with
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// their record-form variants.
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class RecFormRel;
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// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
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// FMA instruction forms with their corresponding factor-killing forms.
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class AltVSXFMARel {
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bit IsVSXFMAAlt = 0;
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}
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//===----------------------------------------------------------------------===//
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// Relation Map Definitions.
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//===----------------------------------------------------------------------===//
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def getRecordFormOpcode : InstrMapping {
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let FilterClass = "RecFormRel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName", "Interpretation64Bit"];
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// Instructions with the same RC value form a column.
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let ColFields = ["RC"];
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|
// The key column are the non-record-form instructions.
|
|
let KeyCol = ["0"];
|
|
// Value columns RC=1
|
|
let ValueCols = [["1"]];
|
|
}
|
|
|
|
def getNonRecordFormOpcode : InstrMapping {
|
|
let FilterClass = "RecFormRel";
|
|
// Instructions with the same BaseName and Interpretation64Bit values
|
|
// form a row.
|
|
let RowFields = ["BaseName", "Interpretation64Bit"];
|
|
// Instructions with the same RC value form a column.
|
|
let ColFields = ["RC"];
|
|
// The key column are the record-form instructions.
|
|
let KeyCol = ["1"];
|
|
// Value columns are RC=0
|
|
let ValueCols = [["0"]];
|
|
}
|
|
|
|
def getAltVSXFMAOpcode : InstrMapping {
|
|
let FilterClass = "AltVSXFMARel";
|
|
// Instructions with the same BaseName value form a row.
|
|
let RowFields = ["BaseName"];
|
|
// Instructions with the same IsVSXFMAAlt value form a column.
|
|
let ColFields = ["IsVSXFMAAlt"];
|
|
// The key column are the (default) addend-killing instructions.
|
|
let KeyCol = ["0"];
|
|
// Value columns IsVSXFMAAlt=1
|
|
let ValueCols = [["1"]];
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "PPCRegisterInfo.td"
|
|
include "PPCSchedule.td"
|
|
include "GISel/PPCRegisterBanks.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// PowerPC processors supported.
|
|
//
|
|
|
|
def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
|
|
FeatureMFTB]>;
|
|
def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureICBT, FeatureBookE,
|
|
FeatureMSYNC, FeatureMFTB]>;
|
|
def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureICBT, FeatureBookE,
|
|
FeatureMSYNC, FeatureMFTB]>;
|
|
def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
|
|
def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
|
|
FeatureMFTB]>;
|
|
def : Processor<"603", G3Itineraries, [Directive603,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"603e", G3Itineraries, [Directive603,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"603ev", G3Itineraries, [Directive603,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"604", G3Itineraries, [Directive604,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"604e", G3Itineraries, [Directive604,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"620", G3Itineraries, [Directive620,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"750", G4Itineraries, [Directive750,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"g3", G3Itineraries, [Directive750,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
FeatureMFTB]>;
|
|
|
|
def : ProcessorModel<"970", G5Model,
|
|
[Directive970, FeatureAltivec,
|
|
FeatureMFOCRF, FeatureFSqrt,
|
|
FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
|
|
Feature64Bit /*, Feature64BitRegs */,
|
|
FeatureMFTB]>;
|
|
def : ProcessorModel<"g5", G5Model,
|
|
[Directive970, FeatureAltivec,
|
|
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
|
|
FeatureFRES, FeatureFRSQRTE,
|
|
Feature64Bit /*, Feature64BitRegs */,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"e500", PPCE500Model,
|
|
[DirectiveE500,
|
|
FeatureICBT, FeatureBookE,
|
|
FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
|
|
def : ProcessorModel<"e500mc", PPCE500mcModel,
|
|
[DirectiveE500mc,
|
|
FeatureSTFIWX, FeatureICBT, FeatureBookE,
|
|
FeatureISEL, FeatureMFTB]>;
|
|
def : ProcessorModel<"e5500", PPCE5500Model,
|
|
[DirectiveE5500, FeatureMFOCRF, Feature64Bit,
|
|
FeatureSTFIWX, FeatureICBT, FeatureBookE,
|
|
FeatureISEL, FeatureMFTB]>;
|
|
def : ProcessorModel<"a2", PPCA2Model,
|
|
[DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
|
|
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
|
|
FeatureSTFIWX, FeatureLFIWAX,
|
|
FeatureFPRND, FeatureFPCVT, FeatureISEL,
|
|
FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
|
|
Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
|
|
def : ProcessorModel<"pwr3", G5Model,
|
|
[DirectivePwr3, FeatureAltivec,
|
|
FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
|
|
FeatureSTFIWX, Feature64Bit]>;
|
|
def : ProcessorModel<"pwr4", G5Model,
|
|
[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
|
|
FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
|
|
FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
|
|
def : ProcessorModel<"pwr5", G5Model,
|
|
[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
|
|
FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES,
|
|
FeatureSTFIWX, Feature64Bit,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"pwr5x", G5Model,
|
|
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
|
|
FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES,
|
|
FeatureSTFIWX, FeatureFPRND, Feature64Bit,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"pwr6", G5Model,
|
|
[DirectivePwr6, FeatureAltivec,
|
|
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
|
|
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
|
|
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
|
|
FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"pwr6x", G5Model,
|
|
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
|
|
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
|
|
FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
|
|
FeatureFPRND, Feature64Bit,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
|
|
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
|
|
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
|
|
// No scheduler model yet.
|
|
def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>;
|
|
// No scheduler model for future CPU.
|
|
def : ProcessorModel<"future", NoSchedModel,
|
|
ProcessorFeatures.FutureFeatures>;
|
|
def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
|
|
FeatureMFTB]>;
|
|
def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
|
|
FeatureMFTB]>;
|
|
def : ProcessorModel<"ppc64", G5Model,
|
|
[Directive64, FeatureAltivec,
|
|
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureSTFIWX,
|
|
Feature64Bit /*, Feature64BitRegs */,
|
|
FeatureMFTB]>;
|
|
def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Conventions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "PPCCallingConv.td"
|
|
|
|
def PPCInstrInfo : InstrInfo {
|
|
let isLittleEndianEncoding = 1;
|
|
|
|
// FIXME: Unset this when no longer needed!
|
|
let decodePositionallyEncodedOperands = 1;
|
|
|
|
let noNamedPositionallyEncodedOperands = 1;
|
|
}
|
|
|
|
def PPCAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
int PassSubtarget = 1;
|
|
int Variant = 0;
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
def PPCAsmParser : AsmParser {
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
def PPCAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
|
|
// We do not use hard coded registers in asm strings. However, some
|
|
// InstAlias definitions use immediate literals. Set RegisterPrefix
|
|
// so that those are not misinterpreted as registers.
|
|
string RegisterPrefix = "%";
|
|
string BreakCharacters = ".";
|
|
}
|
|
|
|
def PPC : Target {
|
|
// Information about the instructions.
|
|
let InstructionSet = PPCInstrInfo;
|
|
|
|
let AssemblyWriters = [PPCAsmWriter];
|
|
let AssemblyParsers = [PPCAsmParser];
|
|
let AssemblyParserVariants = [PPCAsmParserVariant];
|
|
let AllowRegisterRenaming = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pfm Counters
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "PPCPfmCounters.td"
|