429 lines
15 KiB
C++
429 lines
15 KiB
C++
//=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is looks at a packet and tries to form compound insns
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCShuffler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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using namespace Hexagon;
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#define DEBUG_TYPE "hexagon-mccompound"
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enum OpcodeIndex {
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fp0_jump_nt = 0,
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fp0_jump_t,
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fp1_jump_nt,
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fp1_jump_t,
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tp0_jump_nt,
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tp0_jump_t,
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tp1_jump_nt,
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tp1_jump_t
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};
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static const unsigned tstBitOpcode[8] = {
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J4_tstbit0_fp0_jump_nt, J4_tstbit0_fp0_jump_t, J4_tstbit0_fp1_jump_nt,
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J4_tstbit0_fp1_jump_t, J4_tstbit0_tp0_jump_nt, J4_tstbit0_tp0_jump_t,
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J4_tstbit0_tp1_jump_nt, J4_tstbit0_tp1_jump_t};
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static const unsigned cmpeqBitOpcode[8] = {
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J4_cmpeq_fp0_jump_nt, J4_cmpeq_fp0_jump_t, J4_cmpeq_fp1_jump_nt,
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J4_cmpeq_fp1_jump_t, J4_cmpeq_tp0_jump_nt, J4_cmpeq_tp0_jump_t,
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J4_cmpeq_tp1_jump_nt, J4_cmpeq_tp1_jump_t};
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static const unsigned cmpgtBitOpcode[8] = {
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J4_cmpgt_fp0_jump_nt, J4_cmpgt_fp0_jump_t, J4_cmpgt_fp1_jump_nt,
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J4_cmpgt_fp1_jump_t, J4_cmpgt_tp0_jump_nt, J4_cmpgt_tp0_jump_t,
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J4_cmpgt_tp1_jump_nt, J4_cmpgt_tp1_jump_t};
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static const unsigned cmpgtuBitOpcode[8] = {
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J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_fp0_jump_t, J4_cmpgtu_fp1_jump_nt,
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J4_cmpgtu_fp1_jump_t, J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_tp0_jump_t,
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J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_tp1_jump_t};
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static const unsigned cmpeqiBitOpcode[8] = {
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J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_fp0_jump_t, J4_cmpeqi_fp1_jump_nt,
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J4_cmpeqi_fp1_jump_t, J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_tp0_jump_t,
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J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_tp1_jump_t};
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static const unsigned cmpgtiBitOpcode[8] = {
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J4_cmpgti_fp0_jump_nt, J4_cmpgti_fp0_jump_t, J4_cmpgti_fp1_jump_nt,
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J4_cmpgti_fp1_jump_t, J4_cmpgti_tp0_jump_nt, J4_cmpgti_tp0_jump_t,
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J4_cmpgti_tp1_jump_nt, J4_cmpgti_tp1_jump_t};
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static const unsigned cmpgtuiBitOpcode[8] = {
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J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_fp0_jump_t, J4_cmpgtui_fp1_jump_nt,
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J4_cmpgtui_fp1_jump_t, J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_tp0_jump_t,
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J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_tp1_jump_t};
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static const unsigned cmpeqn1BitOpcode[8] = {
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J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_fp1_jump_nt,
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J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_tp0_jump_t,
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J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_tp1_jump_t};
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static const unsigned cmpgtn1BitOpcode[8] = {
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J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_fp1_jump_nt,
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J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_tp0_jump_t,
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J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_tp1_jump_t,
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};
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// enum HexagonII::CompoundGroup
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static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) {
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unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
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switch (MI.getOpcode()) {
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default:
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return HexagonII::HCG_None;
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//
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// Compound pairs.
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// "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
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// "Rd16=#U6 ; jump #r9:2"
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// "Rd16=Rs16 ; jump #r9:2"
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//
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case Hexagon::C2_cmpeq:
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case Hexagon::C2_cmpgt:
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case Hexagon::C2_cmpgtu:
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if (IsExtended)
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return HexagonII::HCG_None;
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DstReg = MI.getOperand(0).getReg();
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Src1Reg = MI.getOperand(1).getReg();
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Src2Reg = MI.getOperand(2).getReg();
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if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
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HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
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HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg))
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return HexagonII::HCG_A;
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break;
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case Hexagon::C2_cmpeqi:
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case Hexagon::C2_cmpgti:
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case Hexagon::C2_cmpgtui:
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if (IsExtended)
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return HexagonII::HCG_None;
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// P0 = cmp.eq(Rs,#u2)
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
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HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
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(HexagonMCInstrInfo::inRange<5>(MI, 2) ||
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HexagonMCInstrInfo::minConstant(MI, 2) == -1))
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return HexagonII::HCG_A;
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break;
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case Hexagon::A2_tfr:
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if (IsExtended)
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return HexagonII::HCG_None;
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// Rd = Rs
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
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HexagonMCInstrInfo::isIntRegForSubInst(SrcReg))
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return HexagonII::HCG_A;
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break;
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case Hexagon::A2_tfrsi:
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if (IsExtended)
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return HexagonII::HCG_None;
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// Rd = #u6
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DstReg = MI.getOperand(0).getReg();
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if (HexagonMCInstrInfo::minConstant(MI, 1) <= 63 &&
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HexagonMCInstrInfo::minConstant(MI, 1) >= 0 &&
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HexagonMCInstrInfo::isIntRegForSubInst(DstReg))
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return HexagonII::HCG_A;
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break;
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case Hexagon::S2_tstbit_i:
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if (IsExtended)
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return HexagonII::HCG_None;
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DstReg = MI.getOperand(0).getReg();
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Src1Reg = MI.getOperand(1).getReg();
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if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
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HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
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HexagonMCInstrInfo::minConstant(MI, 2) == 0)
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return HexagonII::HCG_A;
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break;
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// The fact that .new form is used pretty much guarantees
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// that predicate register will match. Nevertheless,
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// there could be some false positives without additional
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// checking.
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case Hexagon::J2_jumptnew:
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case Hexagon::J2_jumpfnew:
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case Hexagon::J2_jumptnewpt:
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case Hexagon::J2_jumpfnewpt:
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Src1Reg = MI.getOperand(0).getReg();
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if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
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return HexagonII::HCG_B;
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break;
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// Transfer and jump:
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// Rd=#U6 ; jump #r9:2
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// Rd=Rs ; jump #r9:2
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// Do not test for jump range here.
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case Hexagon::J2_jump:
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case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
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return HexagonII::HCG_C;
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break;
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}
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return HexagonII::HCG_None;
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}
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/// getCompoundOp - Return the index from 0-7 into the above opcode lists.
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static unsigned getCompoundOp(MCInst const &HMCI) {
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const MCOperand &Predicate = HMCI.getOperand(0);
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unsigned PredReg = Predicate.getReg();
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assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
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(PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
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switch (HMCI.getOpcode()) {
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default:
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llvm_unreachable("Expected match not found.\n");
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break;
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case Hexagon::J2_jumpfnew:
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return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt;
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case Hexagon::J2_jumpfnewpt:
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return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t;
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case Hexagon::J2_jumptnew:
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return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt;
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case Hexagon::J2_jumptnewpt:
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return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
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}
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}
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static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L,
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MCInst const &R) {
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MCInst *CompoundInsn = nullptr;
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unsigned compoundOpcode;
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MCOperand Rs, Rt;
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int64_t Value;
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bool Success;
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switch (L.getOpcode()) {
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default:
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LLVM_DEBUG(dbgs() << "Possible compound ignored\n");
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return CompoundInsn;
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case Hexagon::A2_tfrsi:
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Rt = L.getOperand(0);
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compoundOpcode = J4_jumpseti;
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rt);
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CompoundInsn->addOperand(L.getOperand(1)); // Immediate
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CompoundInsn->addOperand(R.getOperand(0)); // Jump target
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break;
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case Hexagon::A2_tfr:
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Rt = L.getOperand(0);
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Rs = L.getOperand(1);
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compoundOpcode = J4_jumpsetr;
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rt);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(R.getOperand(0)); // Jump target.
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break;
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case Hexagon::C2_cmpeq:
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LLVM_DEBUG(dbgs() << "CX: C2_cmpeq\n");
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Rs = L.getOperand(1);
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Rt = L.getOperand(2);
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compoundOpcode = cmpeqBitOpcode[getCompoundOp(R)];
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(Rt);
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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case Hexagon::C2_cmpgt:
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LLVM_DEBUG(dbgs() << "CX: C2_cmpgt\n");
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Rs = L.getOperand(1);
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Rt = L.getOperand(2);
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compoundOpcode = cmpgtBitOpcode[getCompoundOp(R)];
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(Rt);
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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case Hexagon::C2_cmpgtu:
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LLVM_DEBUG(dbgs() << "CX: C2_cmpgtu\n");
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Rs = L.getOperand(1);
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Rt = L.getOperand(2);
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compoundOpcode = cmpgtuBitOpcode[getCompoundOp(R)];
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(Rt);
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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case Hexagon::C2_cmpeqi:
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LLVM_DEBUG(dbgs() << "CX: C2_cmpeqi\n");
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Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
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(void)Success;
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assert(Success);
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if (Value == -1)
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compoundOpcode = cmpeqn1BitOpcode[getCompoundOp(R)];
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else
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compoundOpcode = cmpeqiBitOpcode[getCompoundOp(R)];
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Rs = L.getOperand(1);
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(L.getOperand(2));
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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case Hexagon::C2_cmpgti:
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LLVM_DEBUG(dbgs() << "CX: C2_cmpgti\n");
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Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
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(void)Success;
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assert(Success);
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if (Value == -1)
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compoundOpcode = cmpgtn1BitOpcode[getCompoundOp(R)];
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else
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compoundOpcode = cmpgtiBitOpcode[getCompoundOp(R)];
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Rs = L.getOperand(1);
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(L.getOperand(2));
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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case Hexagon::C2_cmpgtui:
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LLVM_DEBUG(dbgs() << "CX: C2_cmpgtui\n");
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Rs = L.getOperand(1);
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compoundOpcode = cmpgtuiBitOpcode[getCompoundOp(R)];
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(L.getOperand(2));
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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case Hexagon::S2_tstbit_i:
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LLVM_DEBUG(dbgs() << "CX: S2_tstbit_i\n");
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Rs = L.getOperand(1);
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compoundOpcode = tstBitOpcode[getCompoundOp(R)];
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CompoundInsn = Context.createMCInst();
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CompoundInsn->setOpcode(compoundOpcode);
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CompoundInsn->addOperand(Rs);
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CompoundInsn->addOperand(R.getOperand(1));
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break;
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}
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return CompoundInsn;
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}
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/// Non-Symmetrical. See if these two instructions are fit for compound pair.
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static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA,
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MCInst const &MIb, bool IsExtendedB) {
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unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA);
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unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB);
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// We have two candidates - check that this is the same register
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// we are talking about.
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unsigned Opca = MIa.getOpcode();
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if (MIaG == HexagonII::HCG_A && MIbG == HexagonII::HCG_C &&
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(Opca == Hexagon::A2_tfr || Opca == Hexagon::A2_tfrsi))
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return true;
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return ((MIaG == HexagonII::HCG_A && MIbG == HexagonII::HCG_B) &&
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(MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg()));
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}
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static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context,
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MCInst &MCI) {
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assert(HexagonMCInstrInfo::isBundle(MCI));
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bool JExtended = false;
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for (MCInst::iterator J =
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MCI.begin() + HexagonMCInstrInfo::bundleInstructionsOffset;
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J != MCI.end(); ++J) {
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MCInst const *JumpInst = J->getInst();
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if (HexagonMCInstrInfo::isImmext(*JumpInst)) {
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JExtended = true;
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continue;
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}
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if (HexagonMCInstrInfo::getType(MCII, *JumpInst) == HexagonII::TypeJ) {
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// Try to pair with another insn (B)undled with jump.
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bool BExtended = false;
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for (MCInst::iterator B =
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MCI.begin() + HexagonMCInstrInfo::bundleInstructionsOffset;
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B != MCI.end(); ++B) {
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MCInst const *Inst = B->getInst();
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if (JumpInst == Inst)
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continue;
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if (HexagonMCInstrInfo::isImmext(*Inst)) {
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BExtended = true;
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continue;
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}
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LLVM_DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << ","
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<< Inst->getOpcode() << "\n");
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if (isOrderedCompoundPair(*Inst, BExtended, *JumpInst, JExtended)) {
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MCInst *CompoundInsn = getCompoundInsn(Context, *Inst, *JumpInst);
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if (CompoundInsn) {
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LLVM_DEBUG(dbgs() << "B: " << Inst->getOpcode() << ","
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<< JumpInst->getOpcode() << " Compounds to "
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<< CompoundInsn->getOpcode() << "\n");
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J->setInst(CompoundInsn);
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MCI.erase(B);
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return true;
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}
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}
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BExtended = false;
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}
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}
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JExtended = false;
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}
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return false;
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}
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/// tryCompound - Given a bundle check for compound insns when one
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/// is found update the contents fo the bundle with the compound insn.
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/// If a compound instruction is found then the bundle will have one
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/// additional slot.
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void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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MCContext &Context, MCInst &MCI) {
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assert(HexagonMCInstrInfo::isBundle(MCI) &&
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"Non-Bundle where Bundle expected");
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// By definition a compound must have 2 insn.
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if (MCI.size() < 2)
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return;
|
|
|
|
bool StartedValid = llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI);
|
|
|
|
// Create a vector, needed to keep the order of jump instructions.
|
|
MCInst CheckList(MCI);
|
|
|
|
// Look for compounds until none are found, only update the bundle when
|
|
// a compound is found.
|
|
while (lookForCompound(MCII, Context, CheckList)) {
|
|
// Keep the original bundle around in case the shuffle fails.
|
|
MCInst OriginalBundle(MCI);
|
|
|
|
// Need to update the bundle.
|
|
MCI = CheckList;
|
|
|
|
if (StartedValid &&
|
|
!llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI)) {
|
|
LLVM_DEBUG(dbgs() << "Found ERROR\n");
|
|
MCI = OriginalBundle;
|
|
}
|
|
}
|
|
}
|