418 lines
18 KiB
C++
418 lines
18 KiB
C++
//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides AArch64 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64MCTargetDesc.h"
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#include "AArch64ELFStreamer.h"
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#include "AArch64MCAsmInfo.h"
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#include "AArch64WinCOFFStreamer.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "MCTargetDesc/AArch64InstPrinter.h"
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#include "TargetInfo/AArch64TargetInfo.h"
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#include "llvm/DebugInfo/CodeView/CodeView.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#define GET_INSTRINFO_MC_HELPERS
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#include "AArch64GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AArch64GenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "AArch64GenRegisterInfo.inc"
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static MCInstrInfo *createAArch64MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitAArch64MCInstrInfo(X);
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return X;
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}
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static MCSubtargetInfo *
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createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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if (CPU.empty()) {
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CPU = "generic";
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if (TT.isArm64e())
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CPU = "apple-a12";
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}
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return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
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}
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void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
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// Mapping from CodeView to MC register id.
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static const struct {
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codeview::RegisterId CVReg;
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MCPhysReg Reg;
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} RegMap[] = {
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{codeview::RegisterId::ARM64_W0, AArch64::W0},
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{codeview::RegisterId::ARM64_W1, AArch64::W1},
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{codeview::RegisterId::ARM64_W2, AArch64::W2},
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{codeview::RegisterId::ARM64_W3, AArch64::W3},
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{codeview::RegisterId::ARM64_W4, AArch64::W4},
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{codeview::RegisterId::ARM64_W5, AArch64::W5},
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{codeview::RegisterId::ARM64_W6, AArch64::W6},
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{codeview::RegisterId::ARM64_W7, AArch64::W7},
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{codeview::RegisterId::ARM64_W8, AArch64::W8},
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{codeview::RegisterId::ARM64_W9, AArch64::W9},
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{codeview::RegisterId::ARM64_W10, AArch64::W10},
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{codeview::RegisterId::ARM64_W11, AArch64::W11},
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{codeview::RegisterId::ARM64_W12, AArch64::W12},
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{codeview::RegisterId::ARM64_W13, AArch64::W13},
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{codeview::RegisterId::ARM64_W14, AArch64::W14},
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{codeview::RegisterId::ARM64_W15, AArch64::W15},
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{codeview::RegisterId::ARM64_W16, AArch64::W16},
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{codeview::RegisterId::ARM64_W17, AArch64::W17},
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{codeview::RegisterId::ARM64_W18, AArch64::W18},
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{codeview::RegisterId::ARM64_W19, AArch64::W19},
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{codeview::RegisterId::ARM64_W20, AArch64::W20},
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{codeview::RegisterId::ARM64_W21, AArch64::W21},
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{codeview::RegisterId::ARM64_W22, AArch64::W22},
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{codeview::RegisterId::ARM64_W23, AArch64::W23},
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{codeview::RegisterId::ARM64_W24, AArch64::W24},
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{codeview::RegisterId::ARM64_W25, AArch64::W25},
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{codeview::RegisterId::ARM64_W26, AArch64::W26},
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{codeview::RegisterId::ARM64_W27, AArch64::W27},
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{codeview::RegisterId::ARM64_W28, AArch64::W28},
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{codeview::RegisterId::ARM64_W29, AArch64::W29},
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{codeview::RegisterId::ARM64_W30, AArch64::W30},
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{codeview::RegisterId::ARM64_WZR, AArch64::WZR},
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{codeview::RegisterId::ARM64_X0, AArch64::X0},
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{codeview::RegisterId::ARM64_X1, AArch64::X1},
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{codeview::RegisterId::ARM64_X2, AArch64::X2},
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{codeview::RegisterId::ARM64_X3, AArch64::X3},
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{codeview::RegisterId::ARM64_X4, AArch64::X4},
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{codeview::RegisterId::ARM64_X5, AArch64::X5},
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{codeview::RegisterId::ARM64_X6, AArch64::X6},
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{codeview::RegisterId::ARM64_X7, AArch64::X7},
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{codeview::RegisterId::ARM64_X8, AArch64::X8},
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{codeview::RegisterId::ARM64_X9, AArch64::X9},
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{codeview::RegisterId::ARM64_X10, AArch64::X10},
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{codeview::RegisterId::ARM64_X11, AArch64::X11},
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{codeview::RegisterId::ARM64_X12, AArch64::X12},
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{codeview::RegisterId::ARM64_X13, AArch64::X13},
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{codeview::RegisterId::ARM64_X14, AArch64::X14},
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{codeview::RegisterId::ARM64_X15, AArch64::X15},
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{codeview::RegisterId::ARM64_X16, AArch64::X16},
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{codeview::RegisterId::ARM64_X17, AArch64::X17},
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{codeview::RegisterId::ARM64_X18, AArch64::X18},
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{codeview::RegisterId::ARM64_X19, AArch64::X19},
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{codeview::RegisterId::ARM64_X20, AArch64::X20},
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{codeview::RegisterId::ARM64_X21, AArch64::X21},
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{codeview::RegisterId::ARM64_X22, AArch64::X22},
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{codeview::RegisterId::ARM64_X23, AArch64::X23},
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{codeview::RegisterId::ARM64_X24, AArch64::X24},
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{codeview::RegisterId::ARM64_X25, AArch64::X25},
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{codeview::RegisterId::ARM64_X26, AArch64::X26},
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{codeview::RegisterId::ARM64_X27, AArch64::X27},
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{codeview::RegisterId::ARM64_X28, AArch64::X28},
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{codeview::RegisterId::ARM64_FP, AArch64::FP},
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{codeview::RegisterId::ARM64_LR, AArch64::LR},
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{codeview::RegisterId::ARM64_SP, AArch64::SP},
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{codeview::RegisterId::ARM64_ZR, AArch64::XZR},
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{codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
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{codeview::RegisterId::ARM64_S0, AArch64::S0},
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{codeview::RegisterId::ARM64_S1, AArch64::S1},
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{codeview::RegisterId::ARM64_S2, AArch64::S2},
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{codeview::RegisterId::ARM64_S3, AArch64::S3},
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{codeview::RegisterId::ARM64_S4, AArch64::S4},
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{codeview::RegisterId::ARM64_S5, AArch64::S5},
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{codeview::RegisterId::ARM64_S6, AArch64::S6},
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{codeview::RegisterId::ARM64_S7, AArch64::S7},
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{codeview::RegisterId::ARM64_S8, AArch64::S8},
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{codeview::RegisterId::ARM64_S9, AArch64::S9},
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{codeview::RegisterId::ARM64_S10, AArch64::S10},
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{codeview::RegisterId::ARM64_S11, AArch64::S11},
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{codeview::RegisterId::ARM64_S12, AArch64::S12},
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{codeview::RegisterId::ARM64_S13, AArch64::S13},
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{codeview::RegisterId::ARM64_S14, AArch64::S14},
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{codeview::RegisterId::ARM64_S15, AArch64::S15},
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{codeview::RegisterId::ARM64_S16, AArch64::S16},
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{codeview::RegisterId::ARM64_S17, AArch64::S17},
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{codeview::RegisterId::ARM64_S18, AArch64::S18},
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{codeview::RegisterId::ARM64_S19, AArch64::S19},
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{codeview::RegisterId::ARM64_S20, AArch64::S20},
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{codeview::RegisterId::ARM64_S21, AArch64::S21},
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{codeview::RegisterId::ARM64_S22, AArch64::S22},
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{codeview::RegisterId::ARM64_S23, AArch64::S23},
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{codeview::RegisterId::ARM64_S24, AArch64::S24},
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{codeview::RegisterId::ARM64_S25, AArch64::S25},
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{codeview::RegisterId::ARM64_S26, AArch64::S26},
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{codeview::RegisterId::ARM64_S27, AArch64::S27},
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{codeview::RegisterId::ARM64_S28, AArch64::S28},
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{codeview::RegisterId::ARM64_S29, AArch64::S29},
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{codeview::RegisterId::ARM64_S30, AArch64::S30},
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{codeview::RegisterId::ARM64_S31, AArch64::S31},
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{codeview::RegisterId::ARM64_D0, AArch64::D0},
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{codeview::RegisterId::ARM64_D1, AArch64::D1},
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{codeview::RegisterId::ARM64_D2, AArch64::D2},
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{codeview::RegisterId::ARM64_D3, AArch64::D3},
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{codeview::RegisterId::ARM64_D4, AArch64::D4},
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{codeview::RegisterId::ARM64_D5, AArch64::D5},
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{codeview::RegisterId::ARM64_D6, AArch64::D6},
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{codeview::RegisterId::ARM64_D7, AArch64::D7},
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{codeview::RegisterId::ARM64_D8, AArch64::D8},
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{codeview::RegisterId::ARM64_D9, AArch64::D9},
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{codeview::RegisterId::ARM64_D10, AArch64::D10},
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{codeview::RegisterId::ARM64_D11, AArch64::D11},
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{codeview::RegisterId::ARM64_D12, AArch64::D12},
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{codeview::RegisterId::ARM64_D13, AArch64::D13},
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{codeview::RegisterId::ARM64_D14, AArch64::D14},
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{codeview::RegisterId::ARM64_D15, AArch64::D15},
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{codeview::RegisterId::ARM64_D16, AArch64::D16},
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{codeview::RegisterId::ARM64_D17, AArch64::D17},
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{codeview::RegisterId::ARM64_D18, AArch64::D18},
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{codeview::RegisterId::ARM64_D19, AArch64::D19},
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{codeview::RegisterId::ARM64_D20, AArch64::D20},
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{codeview::RegisterId::ARM64_D21, AArch64::D21},
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{codeview::RegisterId::ARM64_D22, AArch64::D22},
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{codeview::RegisterId::ARM64_D23, AArch64::D23},
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{codeview::RegisterId::ARM64_D24, AArch64::D24},
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{codeview::RegisterId::ARM64_D25, AArch64::D25},
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{codeview::RegisterId::ARM64_D26, AArch64::D26},
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{codeview::RegisterId::ARM64_D27, AArch64::D27},
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{codeview::RegisterId::ARM64_D28, AArch64::D28},
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{codeview::RegisterId::ARM64_D29, AArch64::D29},
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{codeview::RegisterId::ARM64_D30, AArch64::D30},
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{codeview::RegisterId::ARM64_D31, AArch64::D31},
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{codeview::RegisterId::ARM64_Q0, AArch64::Q0},
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{codeview::RegisterId::ARM64_Q1, AArch64::Q1},
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{codeview::RegisterId::ARM64_Q2, AArch64::Q2},
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{codeview::RegisterId::ARM64_Q3, AArch64::Q3},
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{codeview::RegisterId::ARM64_Q4, AArch64::Q4},
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{codeview::RegisterId::ARM64_Q5, AArch64::Q5},
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{codeview::RegisterId::ARM64_Q6, AArch64::Q6},
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{codeview::RegisterId::ARM64_Q7, AArch64::Q7},
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{codeview::RegisterId::ARM64_Q8, AArch64::Q8},
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{codeview::RegisterId::ARM64_Q9, AArch64::Q9},
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{codeview::RegisterId::ARM64_Q10, AArch64::Q10},
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{codeview::RegisterId::ARM64_Q11, AArch64::Q11},
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{codeview::RegisterId::ARM64_Q12, AArch64::Q12},
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{codeview::RegisterId::ARM64_Q13, AArch64::Q13},
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{codeview::RegisterId::ARM64_Q14, AArch64::Q14},
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{codeview::RegisterId::ARM64_Q15, AArch64::Q15},
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{codeview::RegisterId::ARM64_Q16, AArch64::Q16},
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{codeview::RegisterId::ARM64_Q17, AArch64::Q17},
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{codeview::RegisterId::ARM64_Q18, AArch64::Q18},
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{codeview::RegisterId::ARM64_Q19, AArch64::Q19},
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{codeview::RegisterId::ARM64_Q20, AArch64::Q20},
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{codeview::RegisterId::ARM64_Q21, AArch64::Q21},
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{codeview::RegisterId::ARM64_Q22, AArch64::Q22},
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{codeview::RegisterId::ARM64_Q23, AArch64::Q23},
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{codeview::RegisterId::ARM64_Q24, AArch64::Q24},
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{codeview::RegisterId::ARM64_Q25, AArch64::Q25},
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{codeview::RegisterId::ARM64_Q26, AArch64::Q26},
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{codeview::RegisterId::ARM64_Q27, AArch64::Q27},
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{codeview::RegisterId::ARM64_Q28, AArch64::Q28},
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{codeview::RegisterId::ARM64_Q29, AArch64::Q29},
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{codeview::RegisterId::ARM64_Q30, AArch64::Q30},
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{codeview::RegisterId::ARM64_Q31, AArch64::Q31},
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};
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for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
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MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
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}
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static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitAArch64MCRegisterInfo(X, AArch64::LR);
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AArch64_MC::initLLVMToCVRegMapping(X);
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return X;
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}
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static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TheTriple,
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const MCTargetOptions &Options) {
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MCAsmInfo *MAI;
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if (TheTriple.isOSBinFormatMachO())
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MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);
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else if (TheTriple.isWindowsMSVCEnvironment())
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MAI = new AArch64MCAsmInfoMicrosoftCOFF();
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else if (TheTriple.isOSBinFormatCOFF())
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MAI = new AArch64MCAsmInfoGNUCOFF();
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else {
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assert(TheTriple.isOSBinFormatELF() && "Invalid target");
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MAI = new AArch64MCAsmInfoELF(TheTriple);
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}
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// Initial state of the frame pointer is SP.
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unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
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MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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if (SyntaxVariant == 0)
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return new AArch64InstPrinter(MAI, MII, MRI);
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if (SyntaxVariant == 1)
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return new AArch64AppleInstPrinter(MAI, MII, MRI);
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return nullptr;
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}
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static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
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std::unique_ptr<MCAsmBackend> &&TAB,
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std::unique_ptr<MCObjectWriter> &&OW,
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std::unique_ptr<MCCodeEmitter> &&Emitter,
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bool RelaxAll) {
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return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
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std::move(Emitter), RelaxAll);
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}
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static MCStreamer *createMachOStreamer(MCContext &Ctx,
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std::unique_ptr<MCAsmBackend> &&TAB,
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std::unique_ptr<MCObjectWriter> &&OW,
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std::unique_ptr<MCCodeEmitter> &&Emitter,
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bool RelaxAll,
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bool DWARFMustBeAtTheEnd) {
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return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
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std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
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/*LabelSections*/ true);
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}
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static MCStreamer *
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createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
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std::unique_ptr<MCObjectWriter> &&OW,
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std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
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bool IncrementalLinkerCompatible) {
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return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
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std::move(Emitter), RelaxAll,
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IncrementalLinkerCompatible);
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}
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namespace {
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class AArch64MCInstrAnalysis : public MCInstrAnalysis {
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public:
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AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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uint64_t &Target) const override {
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// Search for a PC-relative argument.
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// This will handle instructions like bcc (where the first argument is the
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// condition code) and cbz (where it is a register).
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const auto &Desc = Info->get(Inst.getOpcode());
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for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
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if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
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int64_t Imm = Inst.getOperand(i).getImm() * 4;
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Target = Addr + Imm;
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return true;
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}
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}
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return false;
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}
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std::vector<std::pair<uint64_t, uint64_t>>
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findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
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uint64_t GotPltSectionVA,
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const Triple &TargetTriple) const override {
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// Do a lightweight parsing of PLT entries.
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std::vector<std::pair<uint64_t, uint64_t>> Result;
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for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
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Byte += 4) {
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uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
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uint64_t Off = 0;
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// Check for optional bti c that prefixes adrp in BTI enabled entries
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if (Insn == 0xd503245f) {
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Off = 4;
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Insn = support::endian::read32le(PltContents.data() + Byte + Off);
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}
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// Check for adrp.
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if ((Insn & 0x9f000000) != 0x90000000)
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continue;
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Off += 4;
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uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
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(((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
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uint32_t Insn2 =
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support::endian::read32le(PltContents.data() + Byte + Off);
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// Check for: ldr Xt, [Xn, #pimm].
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if (Insn2 >> 22 == 0x3e5) {
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Imm += ((Insn2 >> 10) & 0xfff) << 3;
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Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
|
|
Byte += 4;
|
|
}
|
|
}
|
|
return Result;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
|
|
return new AArch64MCInstrAnalysis(Info);
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() {
|
|
for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
|
|
&getTheAArch64_32Target(), &getTheARM64Target(),
|
|
&getTheARM64_32Target()}) {
|
|
// Register the MC asm info.
|
|
RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
|
|
|
|
// Register the MC instruction info.
|
|
TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
|
|
|
|
// Register the MC register info.
|
|
TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
|
|
|
|
// Register the MC subtarget info.
|
|
TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
|
|
|
|
// Register the MC instruction analyzer.
|
|
TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
|
|
|
|
// Register the MC Code Emitter
|
|
TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
|
|
|
|
// Register the obj streamers.
|
|
TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
|
|
TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
|
|
TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer);
|
|
|
|
// Register the obj target streamer.
|
|
TargetRegistry::RegisterObjectTargetStreamer(
|
|
*T, createAArch64ObjectTargetStreamer);
|
|
|
|
// Register the asm streamer.
|
|
TargetRegistry::RegisterAsmTargetStreamer(*T,
|
|
createAArch64AsmTargetStreamer);
|
|
// Register the MCInstPrinter.
|
|
TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
|
|
}
|
|
|
|
// Register the asm backend.
|
|
for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
|
|
&getTheARM64Target(), &getTheARM64_32Target()})
|
|
TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
|
|
TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
|
|
createAArch64beAsmBackend);
|
|
}
|