158 lines
7.5 KiB
TableGen
158 lines
7.5 KiB
TableGen
//===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 Exynos processors.
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//
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//===----------------------------------------------------------------------===//
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// Auxiliary predicates.
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// Check the shift in arithmetic and logic instructions.
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def ExynosCheckShift : CheckAny<[CheckShiftBy0,
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CheckAll<
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[CheckShiftLSL,
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CheckAny<
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[CheckShiftBy1,
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CheckShiftBy2,
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CheckShiftBy3]>]>]>;
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// Exynos predicates.
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// Identify BLR specifying the LR register as the indirect target register.
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def ExynosBranchLinkLRPred : MCSchedPredicate<
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CheckAll<[CheckOpcode<[BLR]>,
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CheckRegOperand<0, LR>]>>;
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// Identify arithmetic instructions without or with limited extension or shift.
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def ExynosArithFn : TIIPredicate<
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"isExynosArithFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithExtOp.ValidOpcodes,
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MCReturnStatement<
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CheckAny<[CheckExtBy0,
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CheckAll<
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[CheckAny<
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[CheckExtUXTW,
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CheckExtUXTX]>,
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CheckAny<
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[CheckExtBy1,
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CheckExtBy2,
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CheckExtBy3]>]>]>>>,
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MCOpcodeSwitchCase<
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IsArithShiftOp.ValidOpcodes,
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MCReturnStatement<ExynosCheckShift>>,
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MCOpcodeSwitchCase<
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IsArithUnshiftOp.ValidOpcodes,
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MCReturnStatement<TruePred>>,
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MCOpcodeSwitchCase<
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IsArithImmOp.ValidOpcodes,
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MCReturnStatement<TruePred>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
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// Identify logic instructions with limited shift.
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def ExynosLogicFn : TIIPredicate<
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"isExynosLogicFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsLogicShiftOp.ValidOpcodes,
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MCReturnStatement<ExynosCheckShift>>,
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MCOpcodeSwitchCase<
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IsLogicUnshiftOp.ValidOpcodes,
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MCReturnStatement<TruePred>>,
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MCOpcodeSwitchCase<
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IsLogicImmOp.ValidOpcodes,
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MCReturnStatement<TruePred>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
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// Identify more logic instructions with limited shift.
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def ExynosLogicExFn : TIIPredicate<
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"isExynosLogicExFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsLogicShiftOp.ValidOpcodes,
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MCReturnStatement<
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CheckAny<
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[ExynosCheckShift,
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CheckAll<
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[CheckShiftLSL,
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CheckShiftBy8]>]>>>,
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MCOpcodeSwitchCase<
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IsLogicUnshiftOp.ValidOpcodes,
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MCReturnStatement<TruePred>>,
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MCOpcodeSwitchCase<
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IsLogicImmOp.ValidOpcodes,
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MCReturnStatement<TruePred>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;
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// Identify a load or store using the register offset addressing mode
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// with a scaled non-extended register.
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def ExynosScaledIdxFn : TIIPredicate<"isExynosScaledAddr",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsLoadStoreRegOffsetOp.ValidOpcodes,
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MCReturnStatement<
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CheckAny<
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[CheckMemExtSXTW,
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CheckMemExtUXTW,
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CheckMemScaled]>>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
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// Identify FP instructions.
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def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckHForm,
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CheckSForm,
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CheckDForm,
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CheckQForm]>>;
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// Identify 128-bit NEON instructions.
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def ExynosQFormPred : MCSchedPredicate<CheckQForm>;
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// Identify instructions that reset a register efficiently.
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def ExynosResetFn : TIIPredicate<
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"isExynosResetFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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[ADR, ADRP,
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MOVNWi, MOVNXi,
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MOVZWi, MOVZXi],
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MCReturnStatement<TruePred>>,
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MCOpcodeSwitchCase<
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[ORRWri, ORRXri],
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MCReturnStatement<
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CheckAll<
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[CheckIsRegOperand<1>,
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CheckAny<
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[CheckRegOperand<1, WZR>,
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CheckRegOperand<1, XZR>]>]>>>],
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MCReturnStatement<
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CheckAny<
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[IsCopyIdiomFn,
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IsZeroFPIdiomFn]>>>>;
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def ExynosResetPred : MCSchedPredicate<ExynosResetFn>;
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// Identify EXTR as the alias for ROR (immediate).
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def ExynosRotateRightImmPred : MCSchedPredicate<
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CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
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CheckSameRegOperand<1, 2>]>>;
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// Identify cheap arithmetic and logic immediate instructions.
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def ExynosCheapFn : TIIPredicate<
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"isExynosCheapAsMove",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithLogicImmOp.ValidOpcodes,
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MCReturnStatement<TruePred>>],
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MCReturnStatement<
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CheckAny<
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[ExynosArithFn, ExynosResetFn, ExynosLogicFn]>>>>;
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