113 lines
3.9 KiB
C++
113 lines
3.9 KiB
C++
//===---------------------- RetireControlUnit.h -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file simulates the hardware responsible for retiring instructions.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MCA_RETIRE_CONTROL_UNIT_H
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#define LLVM_MCA_RETIRE_CONTROL_UNIT_H
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
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#include "llvm/MCA/Instruction.h"
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#include <vector>
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namespace llvm {
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namespace mca {
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/// This class tracks which instructions are in-flight (i.e., dispatched but not
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/// retired) in the OoO backend.
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//
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/// This class checks on every cycle if/which instructions can be retired.
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/// Instructions are retired in program order.
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/// In the event of an instruction being retired, the pipeline that owns
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/// this RetireControlUnit (RCU) gets notified.
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///
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/// On instruction retired, register updates are all architecturally
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/// committed, and any physicall registers previously allocated for the
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/// retired instruction are freed.
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struct RetireControlUnit : public HardwareUnit {
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// A RUToken is created by the RCU for every instruction dispatched to the
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// schedulers. These "tokens" are managed by the RCU in its token Queue.
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//
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// On every cycle ('cycleEvent'), the RCU iterates through the token queue
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// looking for any token with its 'Executed' flag set. If a token has that
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// flag set, then the instruction has reached the write-back stage and will
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// be retired by the RCU.
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//
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// 'NumSlots' represents the number of entries consumed by the instruction in
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// the reorder buffer. Those entries will become available again once the
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// instruction is retired.
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//
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// Note that the size of the reorder buffer is defined by the scheduling
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// model via field 'NumMicroOpBufferSize'.
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struct RUToken {
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InstRef IR;
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unsigned NumSlots; // Slots reserved to this instruction.
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bool Executed; // True if the instruction is past the WB stage.
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};
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private:
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unsigned NextAvailableSlotIdx;
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unsigned CurrentInstructionSlotIdx;
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unsigned NumROBEntries;
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unsigned AvailableEntries;
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unsigned MaxRetirePerCycle; // 0 means no limit.
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std::vector<RUToken> Queue;
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unsigned normalizeQuantity(unsigned Quantity) const {
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// Some instructions may declare a number of uOps which exceeds the size
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// of the reorder buffer. To avoid problems, cap the amount of slots to
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// the size of the reorder buffer.
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Quantity = std::min(Quantity, NumROBEntries);
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// Further normalize the number of micro opcodes for instructions that
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// declare zero opcodes. This should match the behavior of method
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// reserveSlot().
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return std::max(Quantity, 1U);
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}
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unsigned computeNextSlotIdx() const;
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public:
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RetireControlUnit(const MCSchedModel &SM);
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bool isEmpty() const { return AvailableEntries == NumROBEntries; }
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bool isAvailable(unsigned Quantity = 1) const {
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return AvailableEntries >= normalizeQuantity(Quantity);
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}
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unsigned getMaxRetirePerCycle() const { return MaxRetirePerCycle; }
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// Reserves a number of slots, and returns a new token reference.
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unsigned dispatch(const InstRef &IS);
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// Return the current token from the RCU's circular token queue.
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const RUToken &getCurrentToken() const;
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const RUToken &peekNextToken() const;
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// Advance the pointer to the next token in the circular token queue.
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void consumeCurrentToken();
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// Update the RCU token to represent the executed state.
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void onInstructionExecuted(unsigned TokenID);
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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} // namespace mca
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} // namespace llvm
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#endif // LLVM_MCA_RETIRE_CONTROL_UNIT_H
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