318 lines
12 KiB
C++
318 lines
12 KiB
C++
//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "pseudo-lowering"
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namespace {
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class PseudoLoweringEmitter {
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struct OpData {
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enum MapKind { Operand, Imm, Reg };
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MapKind Kind;
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union {
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unsigned Operand; // Operand number mapped to.
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uint64_t Imm; // Integer immedate value.
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Record *Reg; // Physical register.
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} Data;
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};
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struct PseudoExpansion {
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CodeGenInstruction Source; // The source pseudo instruction definition.
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CodeGenInstruction Dest; // The destination instruction to lower to.
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IndexedMap<OpData> OperandMap;
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PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
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IndexedMap<OpData> &m) :
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Source(s), Dest(d), OperandMap(m) {}
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};
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RecordKeeper &Records;
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// It's overkill to have an instance of the full CodeGenTarget object,
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// but it loads everything on demand, not in the constructor, so it's
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// lightweight in performance, so it works out OK.
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CodeGenTarget Target;
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SmallVector<PseudoExpansion, 64> Expansions;
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unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
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CodeGenInstruction &Insn,
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IndexedMap<OpData> &OperandMap,
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unsigned BaseIdx);
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void evaluateExpansion(Record *Pseudo);
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void emitLoweringEmitter(raw_ostream &o);
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public:
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PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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/// run - Output the pseudo-lowerings.
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void run(raw_ostream &o);
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};
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} // End anonymous namespace
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// FIXME: This pass currently can only expand a pseudo to a single instruction.
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// The pseudo expansion really should take a list of dags, not just
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// a single dag, so we can do fancier things.
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unsigned PseudoLoweringEmitter::
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addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
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IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
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unsigned OpsAdded = 0;
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for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
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if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
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// Physical register reference. Explicit check for the special case
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// "zero_reg" definition.
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if (DI->getDef()->isSubClassOf("Register") ||
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DI->getDef()->getName() == "zero_reg") {
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OperandMap[BaseIdx + i].Kind = OpData::Reg;
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OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
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++OpsAdded;
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continue;
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}
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// Normal operands should always have the same type, or we have a
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// problem.
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// FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
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assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
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// FIXME: Are the message operand types backward?
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if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
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PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', operand type '" + DI->getDef()->getName() +
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"' does not match expansion operand type '" +
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Insn.Operands[BaseIdx + i].Rec->getName() + "'");
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PrintFatalNote(DI->getDef(),
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"Value was assigned at the following location:");
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}
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// Source operand maps to destination operand. The Data element
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// will be filled in later, just set the Kind for now. Do it
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// for each corresponding MachineInstr operand, not just the first.
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for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
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OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
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OpsAdded += Insn.Operands[i].MINumOperands;
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} else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
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OperandMap[BaseIdx + i].Kind = OpData::Imm;
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OperandMap[BaseIdx + i].Data.Imm = II->getValue();
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++OpsAdded;
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} else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
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// Just add the operands recursively. This is almost certainly
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// a constant value for a complex operand (> 1 MI operand).
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unsigned NewOps =
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addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
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OpsAdded += NewOps;
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// Since we added more than one, we also need to adjust the base.
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BaseIdx += NewOps - 1;
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} else
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llvm_unreachable("Unhandled pseudo-expansion argument type!");
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}
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return OpsAdded;
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}
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void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
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LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
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// Validate that the result pattern has the corrent number and types
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// of arguments for the instruction it references.
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DagInit *Dag = Rec->getValueAsDag("ResultInst");
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assert(Dag && "Missing result instruction in pseudo expansion!");
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LLVM_DEBUG(dbgs() << " Result: " << *Dag << "\n");
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DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
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if (!OpDef) {
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PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator is not a record");
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PrintFatalNote(Rec->getValue("ResultInst"),
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"Result was assigned at the following location:");
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}
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Record *Operator = OpDef->getDef();
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if (!Operator->isSubClassOf("Instruction")) {
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PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator '" + Operator->getName() +
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"' is not an instruction");
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PrintFatalNote(Rec->getValue("ResultInst"),
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"Result was assigned at the following location:");
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}
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CodeGenInstruction Insn(Operator);
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if (Insn.isCodeGenOnly || Insn.isPseudo) {
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PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator '" + Operator->getName() +
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"' cannot be a pseudo instruction");
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PrintFatalNote(Rec->getValue("ResultInst"),
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"Result was assigned at the following location:");
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}
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if (Insn.Operands.size() != Dag->getNumArgs()) {
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PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator '" + Operator->getName() +
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"' has the wrong number of operands");
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PrintFatalNote(Rec->getValue("ResultInst"),
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"Result was assigned at the following location:");
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}
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unsigned NumMIOperands = 0;
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for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
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NumMIOperands += Insn.Operands[i].MINumOperands;
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IndexedMap<OpData> OperandMap;
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OperandMap.grow(NumMIOperands);
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addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
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// If there are more operands that weren't in the DAG, they have to
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// be operands that have default values, or we have an error. Currently,
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// Operands that are a subclass of OperandWithDefaultOp have default values.
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// Validate that each result pattern argument has a matching (by name)
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// argument in the source instruction, in either the (outs) or (ins) list.
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// Also check that the type of the arguments match.
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//
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// Record the mapping of the source to result arguments for use by
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// the lowering emitter.
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CodeGenInstruction SourceInsn(Rec);
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StringMap<unsigned> SourceOperands;
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for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
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SourceOperands[SourceInsn.Operands[i].Name] = i;
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LLVM_DEBUG(dbgs() << " Operand mapping:\n");
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for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
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// We've already handled constant values. Just map instruction operands
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// here.
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if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
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continue;
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StringMap<unsigned>::iterator SourceOp =
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SourceOperands.find(Dag->getArgNameStr(i));
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if (SourceOp == SourceOperands.end()) {
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PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', output operand '" + Dag->getArgNameStr(i) +
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"' has no matching source operand");
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PrintFatalNote(Rec->getValue("ResultInst"),
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"Value was assigned at the following location:");
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}
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// Map the source operand to the destination operand index for each
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// MachineInstr operand.
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for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
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OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
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SourceOp->getValue();
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LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i
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<< "\n");
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}
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Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
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}
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void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
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// Emit file header.
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emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
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o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
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<< "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
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<< " const MachineInstr *MI) {\n";
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if (!Expansions.empty()) {
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o << " switch (MI->getOpcode()) {\n"
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<< " default: return false;\n";
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for (auto &Expansion : Expansions) {
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CodeGenInstruction &Source = Expansion.Source;
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CodeGenInstruction &Dest = Expansion.Dest;
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o << " case " << Source.Namespace << "::"
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<< Source.TheDef->getName() << ": {\n"
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<< " MCInst TmpInst;\n"
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<< " MCOperand MCOp;\n"
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<< " TmpInst.setOpcode(" << Dest.Namespace << "::"
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<< Dest.TheDef->getName() << ");\n";
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// Copy the operands from the source instruction.
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// FIXME: Instruction operands with defaults values (predicates and cc_out
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// in ARM, for example shouldn't need explicit values in the
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// expansion DAG.
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unsigned MIOpNo = 0;
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for (const auto &DestOperand : Dest.Operands) {
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o << " // Operand: " << DestOperand.Name << "\n";
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for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
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switch (Expansion.OperandMap[MIOpNo + i].Kind) {
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case OpData::Operand:
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o << " lowerOperand(MI->getOperand("
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<< Source.Operands[Expansion.OperandMap[MIOpNo].Data
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.Operand].MIOperandNo + i
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<< "), MCOp);\n"
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<< " TmpInst.addOperand(MCOp);\n";
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break;
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case OpData::Imm:
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o << " TmpInst.addOperand(MCOperand::createImm("
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<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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break;
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case OpData::Reg: {
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Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
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o << " TmpInst.addOperand(MCOperand::createReg(";
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// "zero_reg" is special.
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if (Reg->getName() == "zero_reg")
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o << "0";
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else
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o << Reg->getValueAsString("Namespace") << "::"
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<< Reg->getName();
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o << "));\n";
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break;
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}
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}
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}
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MIOpNo += DestOperand.MINumOperands;
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}
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if (Dest.Operands.isVariadic) {
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MIOpNo = Source.Operands.size() + 1;
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o << " // variable_ops\n";
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o << " for (unsigned i = " << MIOpNo
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<< ", e = MI->getNumOperands(); i != e; ++i)\n"
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<< " if (lowerOperand(MI->getOperand(i), MCOp))\n"
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<< " TmpInst.addOperand(MCOp);\n";
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}
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o << " EmitToStreamer(OutStreamer, TmpInst);\n"
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<< " break;\n"
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<< " }\n";
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}
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o << " }\n return true;";
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} else
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o << " return false;";
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o << "\n}\n\n";
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}
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void PseudoLoweringEmitter::run(raw_ostream &o) {
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StringRef Classes[] = {"PseudoInstExpansion", "Instruction"};
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std::vector<Record *> Insts =
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Records.getAllDerivedDefinitions(makeArrayRef(Classes));
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// Process the pseudo expansion definitions, validating them as we do so.
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Records.startTimer("Process definitions");
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for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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evaluateExpansion(Insts[i]);
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// Generate expansion code to lower the pseudo to an MCInst of the real
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// instruction.
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Records.startTimer("Emit expansion code");
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emitLoweringEmitter(o);
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}
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namespace llvm {
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void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
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PseudoLoweringEmitter(RK).run(OS);
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}
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} // End llvm namespace
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