141 lines
5.1 KiB
C++
141 lines
5.1 KiB
C++
//===-- Target.cpp ----------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// The PowerPC ExegesisTarget.
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//===----------------------------------------------------------------------===//
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#include "../Target.h"
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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namespace llvm {
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namespace exegesis {
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// Helper to fill a memory operand with a value.
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static void setMemOp(InstructionTemplate &IT, int OpIdx,
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const MCOperand &OpVal) {
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const auto Op = IT.getInstr().Operands[OpIdx];
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assert(Op.isExplicit() && "invalid memory pattern");
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IT.getValueFor(Op) = OpVal;
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}
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#include "PPCGenExegesis.inc"
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namespace {
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class ExegesisPowerPCTarget : public ExegesisTarget {
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public:
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ExegesisPowerPCTarget() : ExegesisTarget(PPCCpuPfmCounters) {}
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private:
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std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
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const APInt &Value) const override;
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bool matchesArch(Triple::ArchType Arch) const override {
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return Arch == Triple::ppc64le;
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}
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unsigned getScratchMemoryRegister(const Triple &) const override;
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void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
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unsigned Offset) const override;
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};
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} // end anonymous namespace
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static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
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switch (RegBitWidth) {
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case 32:
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return PPC::LI;
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case 64:
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return PPC::LI8;
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}
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llvm_unreachable("Invalid Value Width");
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}
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// Generates instruction to load an immediate value into a register.
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static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
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const APInt &Value) {
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if (Value.getBitWidth() > RegBitWidth)
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llvm_unreachable("Value must fit in the Register");
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// We don't really care the value in reg, ignore the 16 bit
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// restriction for now.
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// TODO: make sure we get the exact value in reg if needed.
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return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
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.addReg(Reg)
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.addImm(Value.getZExtValue());
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}
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unsigned
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ExegesisPowerPCTarget::getScratchMemoryRegister(const Triple &TT) const {
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// R13 is reserved as Thread Pointer, we won't use threading in benchmark, so
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// use it as scratch memory register
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return TT.isArch64Bit() ? PPC::X13 : PPC::R13;
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}
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void ExegesisPowerPCTarget::fillMemoryOperands(InstructionTemplate &IT,
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unsigned Reg,
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unsigned Offset) const {
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int MemOpIdx = 0;
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if (IT.getInstr().hasTiedRegisters())
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MemOpIdx = 1;
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int DispOpIdx = MemOpIdx + 1;
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const auto DispOp = IT.getInstr().Operands[DispOpIdx];
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if (DispOp.isReg())
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// We don't really care about the real address in snippets,
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// So hardcode X1 for X-form Memory Operations for simplicity.
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// TODO: materialize the offset into a reggister
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setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1));
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else
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setMemOp(IT, DispOpIdx, MCOperand::createImm(Offset)); // Disp
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setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(Reg)); // BaseReg
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}
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std::vector<MCInst> ExegesisPowerPCTarget::setRegTo(const MCSubtargetInfo &STI,
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unsigned Reg,
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const APInt &Value) const {
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// X11 is optional use in function linkage, should be the least used one
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// Use it as scratch reg to load immediate.
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unsigned ScratchImmReg = PPC::X11;
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if (PPC::GPRCRegClass.contains(Reg))
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return {loadImmediate(Reg, 32, Value)};
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if (PPC::G8RCRegClass.contains(Reg))
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return {loadImmediate(Reg, 64, Value)};
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if (PPC::F4RCRegClass.contains(Reg))
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return {loadImmediate(ScratchImmReg, 64, Value),
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MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)};
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// We don't care the real value in reg, so set 64 bits or duplicate 64 bits
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// for simplicity.
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// TODO: update these if we need a accurate 128 values in registers.
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if (PPC::VRRCRegClass.contains(Reg))
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return {loadImmediate(ScratchImmReg, 64, Value),
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MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(ScratchImmReg)};
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if (PPC::VSRCRegClass.contains(Reg))
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return {loadImmediate(ScratchImmReg, 64, Value),
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MCInstBuilder(PPC::MTVSRDD)
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.addReg(Reg)
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.addReg(ScratchImmReg)
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.addReg(ScratchImmReg)};
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if (PPC::VFRCRegClass.contains(Reg))
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return {loadImmediate(ScratchImmReg, 64, Value),
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MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)};
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// SPE not supported yet
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if (PPC::SPERCRegClass.contains(Reg)) {
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errs() << "Unsupported SPE Reg:" << Reg << "\n";
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return {};
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}
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errs() << "setRegTo is not implemented, results will be unreliable:" << Reg
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<< "\n";
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return {};
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}
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static ExegesisTarget *getTheExegesisPowerPCTarget() {
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static ExegesisPowerPCTarget Target;
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return &Target;
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}
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void InitializePowerPCExegesisTarget() {
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ExegesisTarget::registerTarget(getTheExegesisPowerPCTarget());
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}
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} // namespace exegesis
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} // namespace llvm
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