150 lines
6.1 KiB
C++
150 lines
6.1 KiB
C++
// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
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// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm -S \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// From winnt.h
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#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
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( ((op0 & 1) << 14) | \
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((op1 & 7) << 11) | \
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((crn & 15) << 7) | \
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((crm & 15) << 3) | \
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((op2 & 7) << 0) )
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#define ARM64_CNTVCT ARM64_SYSREG(3,3,14, 0,2) // Generic Timer counter register
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#define ARM64_PMCCNTR_EL0 ARM64_SYSREG(3,3, 9,13,0) // Cycle Count Register [CP15_PMCCNTR]
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#define ARM64_PMSELR_EL0 ARM64_SYSREG(3,3, 9,12,5) // Event Counter Selection Register [CP15_PMSELR]
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#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2) // Event Count Register [CP15_PMXEVCNTR]
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#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8) // Direct Event Count Register [n/a]
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#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2) // Thread ID Register, User Read/Write [CP15_TPIDRURW]
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#define ARM64_TPIDRRO_EL0 ARM64_SYSREG(3,3,13, 0,3) // Thread ID Register, User Read Only [CP15_TPIDRURO]
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#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4) // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
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// From intrin.h
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__int64 _ReadStatusReg(int);
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void _WriteStatusReg(int, __int64);
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void check_ReadWriteStatusReg(__int64 v) {
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__int64 ret;
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ret = _ReadStatusReg(ARM64_CNTVCT);
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// CHECK-ASM: mrs x8, CNTVCT_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
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// CHECK-ASM: mrs x8, PMCCNTR_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_PMSELR_EL0);
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// CHECK-ASM: mrs x8, PMSELR_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
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// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
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// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
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// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
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// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_TPIDR_EL0);
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// CHECK-ASM: mrs x8, TPIDR_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
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// CHECK-ASM: mrs x8, TPIDRRO_EL0
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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ret = _ReadStatusReg(ARM64_TPIDR_EL1);
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// CHECK-ASM: mrs x8, TPIDR_EL1
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// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
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// CHECK-IR-NEXT: store i64 %[[VAR]]
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_WriteStatusReg(ARM64_CNTVCT, v);
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// CHECK-ASM: msr S3_3_C14_C0_2, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_PMCCNTR_EL0, v);
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// CHECK-ASM: msr PMCCNTR_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_PMSELR_EL0, v);
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// CHECK-ASM: msr PMSELR_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
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// CHECK-ASM: msr PMXEVCNTR_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
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// CHECK-ASM: msr PMEVCNTR0_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
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// CHECK-ASM: msr PMEVCNTR1_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
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// CHECK-ASM: msr PMEVCNTR30_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_TPIDR_EL0, v);
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// CHECK-ASM: msr TPIDR_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_TPIDRRO_EL0, v);
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// CHECK-ASM: msr TPIDRRO_EL0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 %[[VAR]])
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_WriteStatusReg(ARM64_TPIDR_EL1, v);
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// CHECK-ASM: msr TPIDR_EL1, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 %[[VAR]])
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}
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// CHECK-IR: ![[MD2]] = !{!"3:3:14:0:2"}
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// CHECK-IR: ![[MD3]] = !{!"3:3:9:13:0"}
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// CHECK-IR: ![[MD4]] = !{!"3:3:9:12:5"}
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// CHECK-IR: ![[MD5]] = !{!"3:3:9:13:2"}
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// CHECK-IR: ![[MD6]] = !{!"3:3:14:8:0"}
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// CHECK-IR: ![[MD7]] = !{!"3:3:14:8:1"}
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// CHECK-IR: ![[MD8]] = !{!"3:3:14:11:6"}
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// CHECK-IR: ![[MD9]] = !{!"3:3:13:0:2"}
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// CHECK-IR: ![[MD10]] = !{!"3:3:13:0:3"}
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// CHECK-IR: ![[MD11]] = !{!"3:0:13:0:4"}
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