320 lines
7.0 KiB
LLVM
320 lines
7.0 KiB
LLVM
; RUN: opt < %s -loop-unswitch -enable-new-pm=0 -verify-loop-info -S < %s 2>&1 | FileCheck %s
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; RUN: opt < %s -loop-unswitch -enable-new-pm=0 -verify-loop-info -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s
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define i32 @test(i32* %A, i1 %C) {
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entry:
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br label %no_exit
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no_exit: ; preds = %no_exit.backedge, %entry
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%i.0.0 = phi i32 [ 0, %entry ], [ %i.0.0.be, %no_exit.backedge ] ; <i32> [#uses=3]
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%gep.upgrd.1 = zext i32 %i.0.0 to i64 ; <i64> [#uses=1]
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%tmp.7 = getelementptr i32, i32* %A, i64 %gep.upgrd.1 ; <i32*> [#uses=4]
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%tmp.13 = load i32, i32* %tmp.7 ; <i32> [#uses=2]
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%tmp.14 = add i32 %tmp.13, 1 ; <i32> [#uses=1]
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store i32 %tmp.14, i32* %tmp.7
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br i1 %C, label %then, label %endif
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then: ; preds = %no_exit
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%tmp.29 = load i32, i32* %tmp.7 ; <i32> [#uses=1]
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%tmp.30 = add i32 %tmp.29, 2 ; <i32> [#uses=1]
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store i32 %tmp.30, i32* %tmp.7
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%inc9 = add i32 %i.0.0, 1 ; <i32> [#uses=2]
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%tmp.112 = icmp ult i32 %inc9, 100000 ; <i1> [#uses=1]
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br i1 %tmp.112, label %no_exit.backedge, label %return
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no_exit.backedge: ; preds = %endif, %then
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%i.0.0.be = phi i32 [ %inc9, %then ], [ %inc, %endif ] ; <i32> [#uses=1]
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br label %no_exit
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endif: ; preds = %no_exit
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%inc = add i32 %i.0.0, 1 ; <i32> [#uses=2]
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%tmp.1 = icmp ult i32 %inc, 100000 ; <i1> [#uses=1]
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br i1 %tmp.1, label %no_exit.backedge, label %return
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return: ; preds = %endif, %then
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ret i32 %tmp.13
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}
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; This simple test would normally unswitch, but should be inhibited by the presence of
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; the noduplicate call.
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; CHECK-LABEL: @test2(
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define i32 @test2(i32* %var) {
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%mem = alloca i32
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store i32 2, i32* %mem
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%c = load i32, i32* %mem
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %c, label %default [
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i32 1, label %inc
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i32 2, label %dec
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]
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inc:
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call void @incf() noreturn nounwind
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br label %loop_begin
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dec:
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; CHECK: call void @decf()
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; CHECK-NOT: call void @decf()
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call void @decf() noreturn nounwind noduplicate
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br label %loop_begin
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default:
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br label %loop_exit
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loop_exit:
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ret i32 0
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; CHECK: }
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}
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; This simple test would normally unswitch, but should be inhibited by the presence of
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; the convergent call that is not control-dependent on the unswitch condition.
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; CHECK-LABEL: @test3(
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define i32 @test3(i32* %var) {
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%mem = alloca i32
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store i32 2, i32* %mem
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%c = load i32, i32* %mem
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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; CHECK: call void @conv()
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; CHECK-NOT: call void @conv()
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call void @conv() convergent
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switch i32 %c, label %default [
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i32 1, label %inc
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i32 2, label %dec
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]
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inc:
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call void @incf() noreturn nounwind
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br label %loop_begin
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dec:
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call void @decf() noreturn nounwind
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br label %loop_begin
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default:
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br label %loop_exit
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loop_exit:
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ret i32 0
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; CHECK: }
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}
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; Make sure we unswitch %a == 0 out of the loop.
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;
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; CHECK: define void @and_i2_as_switch_input(i2
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; CHECK: entry:
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; This is an indication that the loop has been unswitched.
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; CHECK: icmp eq i2 %a, 0
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; CHECK: br
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; There should be no more unswitching after the 1st unswitch.
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; CHECK-NOT: icmp eq
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; CHECK: ret
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define void @and_i2_as_switch_input(i2 %a) {
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entry:
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br label %for.body
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for.body:
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%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
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%and = and i2 %a, %i
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%and1 = and i2 %and, %i
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switch i2 %and1, label %sw.default [
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i2 0, label %sw.bb
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i2 1, label %sw.bb1
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]
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sw.bb:
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br label %sw.epilog
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sw.bb1:
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br label %sw.epilog
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sw.default:
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br label %sw.epilog
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sw.epilog:
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br label %for.inc
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for.inc:
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%inc = add nsw i2 %i, 1
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%cmp = icmp slt i2 %inc, 3
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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; Make sure we unswitch %a == !0 out of the loop.
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;
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; CHECK: define void @or_i2_as_switch_input(i2
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; CHECK: entry:
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; This is an indication that the loop has been unswitched.
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; CHECK: icmp eq i2 %a, -1
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; CHECK: br
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; There should be no more unswitching after the 1st unswitch.
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; CHECK-NOT: icmp eq
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; CHECK: ret
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define void @or_i2_as_switch_input(i2 %a) {
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entry:
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br label %for.body
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for.body:
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%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
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%or = or i2 %a, %i
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%or1 = or i2 %or, %i
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switch i2 %or1, label %sw.default [
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i2 2, label %sw.bb
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i2 3, label %sw.bb1
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]
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sw.bb:
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br label %sw.epilog
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sw.bb1:
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br label %sw.epilog
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sw.default:
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br label %sw.epilog
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sw.epilog:
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br label %for.inc
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for.inc:
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%inc = add nsw i2 %i, 1
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%cmp = icmp slt i2 %inc, 3
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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; Make sure we unswitch %a == !0 out of the loop. Even we do not
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; have it as a case value. Unswitching it out allows us to simplify
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; the or operator chain.
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;
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; CHECK: define void @or_i2_as_switch_input_unswitch_default(i2
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; CHECK: entry:
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; This is an indication that the loop has been unswitched.
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; CHECK: icmp eq i2 %a, -1
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; CHECK: br
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; There should be no more unswitching after the 1st unswitch.
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; CHECK-NOT: icmp eq
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; CHECK: ret
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define void @or_i2_as_switch_input_unswitch_default(i2 %a) {
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entry:
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br label %for.body
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for.body:
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%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
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%or = or i2 %a, %i
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%or1 = or i2 %or, %i
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switch i2 %or1, label %sw.default [
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i2 1, label %sw.bb
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i2 2, label %sw.bb1
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]
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sw.bb:
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br label %sw.epilog
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sw.bb1:
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br label %sw.epilog
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sw.default:
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br label %sw.epilog
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sw.epilog:
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br label %for.inc
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for.inc:
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%inc = add nsw i2 %i, 1
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%cmp = icmp slt i2 %inc, 3
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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; Make sure we don't unswitch, as we can not find an input value %a
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; that will effectively unswitch 0 or 3 out of the loop.
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;
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; CHECK: define void @and_or_i2_as_switch_input(i2
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; CHECK: entry:
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; This is an indication that the loop has NOT been unswitched.
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; CHECK-NOT: icmp
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; CHECK: br
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define void @and_or_i2_as_switch_input(i2 %a) {
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entry:
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br label %for.body
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for.body:
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%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
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%and = and i2 %a, %i
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%or = or i2 %and, %i
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switch i2 %or, label %sw.default [
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i2 0, label %sw.bb
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i2 3, label %sw.bb1
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]
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sw.bb:
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br label %sw.epilog
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sw.bb1:
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br label %sw.epilog
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sw.default:
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br label %sw.epilog
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sw.epilog:
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br label %for.inc
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for.inc:
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%inc = add nsw i2 %i, 1
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%cmp = icmp slt i2 %inc, 3
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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; Make sure we don't unswitch, as we can not find an input value %a
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; that will effectively unswitch true/false out of the loop.
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;
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; CHECK: define void @and_or_i1_as_branch_input(i1
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; CHECK: entry:
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; This is an indication that the loop has NOT been unswitched.
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; CHECK-NOT: icmp
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; CHECK: br
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define void @and_or_i1_as_branch_input(i1 %a) {
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entry:
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br label %for.body
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for.body:
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%i = phi i1 [ 0, %entry ], [ %inc, %for.inc ]
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%and = and i1 %a, %i
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%or = or i1 %and, %i
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br i1 %or, label %sw.bb, label %sw.bb1
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sw.bb:
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br label %sw.epilog
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sw.bb1:
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br label %sw.epilog
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sw.epilog:
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br label %for.inc
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for.inc:
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%inc = add nsw i1 %i, 1
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%cmp = icmp slt i1 %inc, 1
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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declare void @incf() noreturn
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declare void @decf() noreturn
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declare void @conv() convergent
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