229 lines
7.6 KiB
LLVM
229 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -indvars < %s | FileCheck %s
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target datalayout = "n8:16:32:64"
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@G = external global i32
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; Basic case where we know the value of an induction variable along one
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; exit edge, but not another.
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define i32 @test(i32 %n) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* @G
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[HEADER]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[HEADER]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: ret i32 [[N]]
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;
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entry:
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br label %header
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header:
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%iv = phi i32 [0, %entry], [%iv.next, %latch]
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%v = load volatile i32, i32* @G
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%cmp1 = icmp eq i32 %v, 0
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br i1 %cmp1, label %latch, label %exit1
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latch:
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%iv.next = add i32 %iv, 1
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%cmp2 = icmp ult i32 %iv, %n
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br i1 %cmp2, label %header, label %exit2
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exit1:
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ret i32 %iv
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exit2:
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ret i32 %iv
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}
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define i32 @test2(i32 %n) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* @G
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[HEADER]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[HEADER]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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br label %header
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header:
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%iv = phi i32 [0, %entry], [%iv.next, %latch]
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%v = load volatile i32, i32* @G
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%cmp1 = icmp eq i32 %v, 0
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br i1 %cmp1, label %latch, label %exit1
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latch:
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%iv.next = add i32 %iv, 1
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%cmp2 = icmp ult i32 %iv, %n
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br i1 %cmp2, label %header, label %exit2
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exit1:
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ret i32 %iv
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exit2:
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ret i32 %iv.next
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}
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define i32 @neg_wrong_loop(i32 %n) {
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; CHECK-LABEL: @neg_wrong_loop(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WRONG_LOOP:%.*]]
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; CHECK: wrong_loop:
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV2_NEXT:%.*]], [[WRONG_LOOP]] ]
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; CHECK-NEXT: [[IV2_NEXT]] = add i32 [[IV2]], 1
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; CHECK-NEXT: [[UNKNOWN:%.*]] = load volatile i32, i32* @G
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; CHECK-NEXT: [[CMP_UNK:%.*]] = icmp eq i32 [[UNKNOWN]], 0
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; CHECK-NEXT: br i1 [[CMP_UNK]], label [[HEADER_PREHEADER:%.*]], label [[WRONG_LOOP]]
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; CHECK: header.preheader:
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; CHECK-NEXT: [[IV2_LCSSA:%.*]] = phi i32 [ [[IV2]], [[WRONG_LOOP]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[HEADER_PREHEADER]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* @G
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[HEADER]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[HEADER]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: [[EXITVAL:%.*]] = phi i32 [ [[IV2_LCSSA]], [[LATCH]] ]
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; CHECK-NEXT: ret i32 [[EXITVAL]]
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;
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entry:
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br label %wrong_loop
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wrong_loop:
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%iv2 = phi i32 [0, %entry], [%iv2.next, %wrong_loop]
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%iv2.next = add i32 %iv2, 1
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%unknown = load volatile i32, i32* @G
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%cmp_unk = icmp eq i32 %unknown, 0
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br i1 %cmp_unk, label %header.preheader, label %wrong_loop
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header.preheader:
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%iv2.lcssa = phi i32 [%iv2, %wrong_loop]
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br label %header
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header:
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%iv = phi i32 [0, %header.preheader], [%iv.next, %latch]
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%v = load volatile i32, i32* @G
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%cmp1 = icmp eq i32 %v, 0
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br i1 %cmp1, label %latch, label %exit1
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latch:
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%iv.next = add i32 %iv, 1
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%cmp2 = icmp ult i32 %iv, %n
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br i1 %cmp2, label %header, label %exit2
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exit1:
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ret i32 %iv
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exit2:
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%exitval = phi i32 [%iv2.lcssa, %latch]
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ret i32 %exitval
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}
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; TODO: Generalize the code to handle other SCEV expressions
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define i32 @test3(i32 %n) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EXPR:%.*]] = udiv i32 [[IV]], 5
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; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* @G
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[HEADER]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[EXPR_LCSSA:%.*]] = phi i32 [ [[EXPR]], [[HEADER]] ]
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; CHECK-NEXT: ret i32 [[EXPR_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: [[EXPR_LCSSA1:%.*]] = phi i32 [ [[EXPR]], [[LATCH]] ]
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; CHECK-NEXT: ret i32 [[EXPR_LCSSA1]]
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;
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entry:
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br label %header
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header:
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%iv = phi i32 [0, %entry], [%iv.next, %latch]
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%expr = udiv i32 %iv, 5
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%v = load volatile i32, i32* @G
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%cmp1 = icmp eq i32 %v, 0
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br i1 %cmp1, label %latch, label %exit1
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latch:
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%iv.next = add i32 %iv, 1
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%cmp2 = icmp ult i32 %iv, %n
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br i1 %cmp2, label %header, label %exit2
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exit1:
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ret i32 %expr
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exit2:
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ret i32 %expr
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}
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; A slightly more real example where we're searching for either a) the first
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; non-zero element, or b) the end of a memory region.
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define i32 @bounded_find(i32 %n) {
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; CHECK-LABEL: @bounded_find(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, i32* @G, i32 [[IV]]
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; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[ADDR]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[HEADER]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[HEADER]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: ret i32 [[N]]
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;
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entry:
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br label %header
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header:
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%iv = phi i32 [0, %entry], [%iv.next, %latch]
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%addr = getelementptr i32, i32* @G, i32 %iv
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%v = load i32, i32* %addr
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%cmp1 = icmp eq i32 %v, 0
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br i1 %cmp1, label %latch, label %exit1
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latch:
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%iv.next = add i32 %iv, 1
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%cmp2 = icmp ult i32 %iv, %n
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br i1 %cmp2, label %header, label %exit2
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exit1:
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ret i32 %iv
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exit2:
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ret i32 %iv
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}
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