99 lines
3.6 KiB
ArmAsm
99 lines
3.6 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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uqshl z0.b, p0/m, z0.b, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
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// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.b, p0/m, z0.b, #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
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// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.h, p0/m, z0.h, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
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// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.h, p0/m, z0.h, #16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
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// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.s, p0/m, z0.s, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
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// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.s, p0/m, z0.s, #32
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
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// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #32
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.d, p0/m, z0.d, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
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// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.d, p0/m, z0.d, #64
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
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// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #64
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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uqshl z0.b, p0/m, z1.b, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.b, p0/m, z1.b, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Element sizes must match
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uqshl z0.b, p0/m, z0.d, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.b, p0/m, z0.b, z1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.b, p0/m, z0.d, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.d, p0/m, z0.b, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uqshl z0.d, p0/m, z0.b, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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uqshl z0.b, p0/z, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: uqshl z0.b, p0/z, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.b, p8/m, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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uqshl z0.b, p8/m, z0.b, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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