202 lines
5.5 KiB
YAML
202 lines
5.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define i64 @test_zext_i1(i8 %a) {
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%val = trunc i8 %a to i1
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%r = zext i1 %val to i64
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ret i64 %r
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}
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define i64 @test_sext_i8(i8 %val) {
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%r = sext i8 %val to i64
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ret i64 %r
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}
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define i64 @test_sext_i16(i16 %val) {
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%r = sext i16 %val to i64
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ret i64 %r
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}
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define void @anyext_s64_from_s1() { ret void }
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define void @anyext_s64_from_s8() { ret void }
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define void @anyext_s64_from_s16() { ret void }
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define void @anyext_s64_from_s32() { ret void }
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...
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---
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name: test_zext_i1
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: test_zext_i1
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; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
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; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_8bit
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; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
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; ALL: $rax = COPY [[AND64ri8_]]
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; ALL: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s1) = G_TRUNC %0(s8)
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%2(s64) = G_ZEXT %1(s1)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: test_sext_i8
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: test_sext_i8
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; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
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; ALL: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]]
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; ALL: $rax = COPY [[MOVSX64rr8_]]
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; ALL: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s64) = G_SEXT %0(s8)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_sext_i16
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: test_sext_i16
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; ALL: [[COPY:%[0-9]+]]:gr16 = COPY $di
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; ALL: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]]
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; ALL: $rax = COPY [[MOVSX64rr16_]]
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; ALL: RET 0, implicit $rax
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%0(s16) = COPY $di
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%1(s64) = G_SEXT %0(s16)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: anyext_s64_from_s1
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: anyext_s64_from_s1
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; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
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; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
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; ALL: $rax = COPY [[SUBREG_TO_REG]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s1) = G_TRUNC %0(s64)
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%2(s64) = G_ANYEXT %1(s1)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: anyext_s64_from_s8
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: anyext_s64_from_s8
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; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
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; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; ALL: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
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; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr8_]], %subreg.sub_32bit
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; ALL: $rax = COPY [[SUBREG_TO_REG]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s8) = G_TRUNC %0(s64)
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%2(s64) = G_ANYEXT %1(s8)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: anyext_s64_from_s16
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: anyext_s64_from_s16
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; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; ALL: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
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; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr16_]], %subreg.sub_32bit
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; ALL: $rax = COPY [[SUBREG_TO_REG]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s16) = G_TRUNC %0(s64)
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%2(s64) = G_ANYEXT %1(s16)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: anyext_s64_from_s32
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; ALL-LABEL: name: anyext_s64_from_s32
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; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
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; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32bit
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; ALL: $rax = COPY [[INSERT_SUBREG]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s32) = G_TRUNC %0(s64)
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%2(s64) = G_ANYEXT %1(s32)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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