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llvm-for-llvmta/test/CodeGen/VE/VELIntrinsics/vrmin.ll

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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test vector minimum intrinsic instructions
;;;
;;; Note:
;;; We test VRMIN*vl and VRMIN*vl_v instructions.
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswfstsx_vvl(<256 x double> %0) {
; CHECK-LABEL: vrminswfstsx_vvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.fst.sx %v0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstsx.vvl(<256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswfstsx.vvl(<256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswfstsx_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vrminswfstsx_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.fst.sx %v1, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswfstsx.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswlstsx_vvl(<256 x double> %0) {
; CHECK-LABEL: vrminswlstsx_vvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.lst.sx %v0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstsx.vvl(<256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswlstsx.vvl(<256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswlstsx_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vrminswlstsx_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.lst.sx %v1, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswlstsx.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswfstzx_vvl(<256 x double> %0) {
; CHECK-LABEL: vrminswfstzx_vvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.fst.zx %v0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstzx.vvl(<256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswfstzx.vvl(<256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswfstzx_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vrminswfstzx_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.fst.zx %v1, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswfstzx.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswlstzx_vvl(<256 x double> %0) {
; CHECK-LABEL: vrminswlstzx_vvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.lst.zx %v0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstzx.vvl(<256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswlstzx.vvl(<256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminswlstzx_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vrminswlstzx_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.w.lst.zx %v1, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminswlstzx.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminslfst_vvl(<256 x double> %0) {
; CHECK-LABEL: vrminslfst_vvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.l.fst %v0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vrminslfst.vvl(<256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminslfst.vvl(<256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminslfst_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vrminslfst_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.l.fst %v1, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vrminslfst.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminslfst.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminsllst_vvl(<256 x double> %0) {
; CHECK-LABEL: vrminsllst_vvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.l.lst %v0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vrminsllst.vvl(<256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminsllst.vvl(<256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vrminsllst_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vrminsllst_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vrmins.l.lst %v1, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vrminsllst.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vrminsllst.vvvl(<256 x double>, <256 x double>, i32)
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