315 lines
12 KiB
LLVM
315 lines
12 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector floating compare and select minimum intrinsic instructions
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;;;
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;;; Note:
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;;; We test VFMIN*vvl, VFMIN*vvl_v, VFMIN*rvl, VFMIN*rvl_v, VFMIN*vvml_v,
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;;; VFMIN*rvml_v, PVFMIN*vvl, PVFMIN*vvl_v, PVFMIN*rvl, PVFMIN*rvl_v,
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;;; PVFMIN*vvml_v, and PVFMIN*rvml_v instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmind_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vfmind_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmin.d %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vfmind.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmind.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmind_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vfmind_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmin.d %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vfmind.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmind.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmind_vsvl(double %0, <256 x double> %1) {
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; CHECK-LABEL: vfmind_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmin.d %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vfmind.vsvl(double %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmind.vsvl(double, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmind_vsvvl(double %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vfmind_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmin.d %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vfmind.vsvvl(double %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmind.vsvvl(double, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmind_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vfmind_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmin.d %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vfmind.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmind.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmind_vsvmvl(double %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vfmind_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmin.d %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vfmind.vsvmvl(double %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmind.vsvmvl(double, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmins_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vfmins_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmin.s %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vfmins.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmins.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmins_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vfmins_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmin.s %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vfmins.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmins.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmins_vsvl(float %0, <256 x double> %1) {
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; CHECK-LABEL: vfmins_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmin.s %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vfmins.vsvl(float %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmins.vsvl(float, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmins_vsvvl(float %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vfmins_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmin.s %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vfmins.vsvvl(float %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmins.vsvvl(float, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmins_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vfmins_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vfmin.s %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vfmins.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmins.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vfmins_vsvmvl(float %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vfmins_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmin.s %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vfmins.vsvmvl(float %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vfmins.vsvmvl(float, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pvfmin_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: pvfmin_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfmin %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.pvfmin.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pvfmin.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pvfmin_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: pvfmin_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfmin %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.pvfmin.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pvfmin.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pvfmin_vsvl(i64 %0, <256 x double> %1) {
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; CHECK-LABEL: pvfmin_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfmin %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.pvfmin.vsvl(i64 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pvfmin.vsvl(i64, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pvfmin_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: pvfmin_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfmin %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.pvfmin.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pvfmin.vsvvl(i64, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pvfmin_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: pvfmin_vvvMvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfmin %v2, %v0, %v1, %vm2
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.pvfmin.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pvfmin.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pvfmin_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: pvfmin_vsvMvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfmin %v1, %s0, %v0, %vm2
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.pvfmin.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pvfmin.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)
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