208 lines
8.7 KiB
YAML
208 lines
8.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
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entry:
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%cmp8 = icmp eq i32 %N, 0
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br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %N)
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br label %for.body
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for.cond.cleanup: ; preds = %for.end, %entry
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ret void
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for.body: ; preds = %for.end, %for.body.preheader
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%lsr.iv4 = phi i32* [ %b, %for.body.preheader ], [ %scevgep5, %for.end ]
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%lsr.iv2 = phi i32* [ %c, %for.body.preheader ], [ %scevgep3, %for.end ]
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%lsr.iv1 = phi i32* [ %a, %for.body.preheader ], [ %scevgep, %for.end ]
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%lsr.iv = phi i32 [ %start, %for.body.preheader ], [ %lsr.iv.next, %for.end ]
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%size = call i32 @llvm.arm.space(i32 3072, i32 undef)
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%0 = load i32, i32* %lsr.iv4, align 4
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%1 = load i32, i32* %lsr.iv2, align 4
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%mul = mul nsw i32 %1, %0
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store i32 %mul, i32* %lsr.iv1, align 4
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%cmp = icmp ne i32 %0, 0
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br i1 %cmp, label %middle.block, label %for.end
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middle.block: ; preds = %for.body
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%div = udiv i32 %1, %0
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store i32 %div, i32* %lsr.iv1, align 4
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%size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef)
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br label %for.end
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for.end: ; preds = %middle.block, %for.body
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%scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
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%scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 1
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%scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
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%lsr.iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
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%exitcond = icmp eq i32 %lsr.iv.next, 0
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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; Function Attrs: nounwind
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declare i32 @llvm.arm.space(i32 immarg, i32) #0
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.start.loop.iterations.i32(i32) #1
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #0
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attributes #0 = { nounwind }
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attributes #1 = { noduplicate nounwind }
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...
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---
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name: size_limit
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: size_limit
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
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; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
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; CHECK: bb.1.for.body.preheader:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3
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; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
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; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
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; CHECK: bb.2.for.end:
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; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2
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; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
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; CHECK: t2B %bb.5, 14 /* CC::al */, $noreg
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; CHECK: bb.3.for.body:
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; CHECK: successors: %bb.4(0x50000000), %bb.2(0x30000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2
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; CHECK: dead renamable $r3 = SPACE 3072, undef renamable $r0
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; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv4)
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; CHECK: renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv2)
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; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg
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; CHECK: tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.lsr.iv1)
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; CHECK: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.4.middle.block:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
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; CHECK: renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg
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; CHECK: tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.lsr.iv1)
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; CHECK: dead renamable $r3 = SPACE 1024, undef renamable $r0
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; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
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; CHECK: bb.5.for.cond.cleanup:
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $r4, $lr
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frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r4, -8
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tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
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t2IT 0, 8, implicit-def $itstate
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tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
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bb.1.for.body.preheader:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $r4, $lr
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$lr = tMOVr $r3, 14, $noreg
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$lr = t2DoLoopStart killed $r3
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tB %bb.2, 14, $noreg
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bb.2.for.end:
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successors: %bb.5(0x04000000), %bb.3(0x7c000000)
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liveins: $lr, $r0, $r1, $r2
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renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
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renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg
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renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
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t2B %bb.5, 14, $noreg
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bb.3.for.body:
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successors: %bb.4(0x50000000), %bb.2(0x30000000)
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liveins: $lr, $r0, $r1, $r2
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dead renamable $r3 = SPACE 3072, undef renamable $r0
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renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load 4 from %ir.lsr.iv4)
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renamable $r12 = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load 4 from %ir.lsr.iv2)
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tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
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renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14, $noreg
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tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1)
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t2Bcc %bb.2, 0, killed $cpsr
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bb.4.middle.block:
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successors: %bb.2(0x80000000)
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liveins: $lr, $r0, $r1, $r2, $r3, $r12
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renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg
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tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1)
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dead renamable $r3 = SPACE 1024, undef renamable $r0
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t2B %bb.2, 14, $noreg
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bb.5.for.cond.cleanup:
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tPOP_RET 14, $noreg, def $r4, def $pc
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...
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