llvm-for-llvmta/test/CodeGen/SystemZ/cond-move-regalloc-hints-02...

55 lines
1.5 KiB
YAML

# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -start-before=greedy %s -o - \
# RUN: | FileCheck %s
#
# Test that two-address reg alloc hints are given so that a SELR becomes LOCR.
--- |
define i32 @fun(i32 %arg, i32 %arg1, i32 %arg2, i32* %arg3) { ret i32 0 }
declare void @foo(i32)
...
# CHECK-LABEL: fun
# CHECK: locr
---
name: fun
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32bit }
- { id: 1, class: gr32bit }
- { id: 2, class: gr32bit }
- { id: 3, class: gr32bit }
- { id: 4, class: gr64bit }
- { id: 5, class: grx32bit }
- { id: 6, class: grx32bit }
- { id: 7, class: addr64bit }
- { id: 8, class: grx32bit }
- { id: 9, class: grx32bit }
- { id: 10, class: gr64bit }
- { id: 11, class: gr32bit }
frameInfo:
maxAlignment: 1
hasCalls: true
machineFunctionInfo: {}
body: |
bb.0:
%5:grx32bit = LHIMux 88
%8:grx32bit = LHIMux 77
%9:grx32bit = LHIMux 66
bb.1:
%6:grx32bit = LLCMux undef %7:addr64bit, 0, $noreg :: (load 1 from `i8* undef`)
CHIMux %6, 1, implicit-def $cc
%11:gr32bit = SELRMux %8, %9:grx32bit, 14, 6, implicit killed $cc
CHIMux %6, 2, implicit-def $cc
%0:gr32bit = SELRMux %11, %5, 14, 8, implicit killed $cc
ADJCALLSTACKDOWN 0, 0
%10:gr64bit = LGFR %0
$r2d = COPY %10
CallBRASL @foo, killed $r2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc
ADJCALLSTACKUP 0, 0
J %bb.1
...