102 lines
3.8 KiB
LLVM
102 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
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; RUN: -verify-machineinstrs | FileCheck %s
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; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
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; RUN: -verify-machineinstrs | FileCheck %s
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define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vscale x 4 x i16> *%pb) nounwind {
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; CHECK-LABEL: vadd_vint16m1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a3, zero, e16,m1,ta,mu
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; CHECK-NEXT: vle16.v v25, (a1)
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; CHECK-NEXT: vle16.v v26, (a2)
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; CHECK-NEXT: vadd.vv v25, v25, v26
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; CHECK-NEXT: vse16.v v25, (a0)
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; CHECK-NEXT: ret
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%va = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pa
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%vb = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pb
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%vc = add <vscale x 4 x i16> %va, %vb
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store <vscale x 4 x i16> %vc, <vscale x 4 x i16> *%pc
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ret void
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}
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define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vscale x 8 x i16> *%pb) nounwind {
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; CHECK-LABEL: vadd_vint16m2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu
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; CHECK-NEXT: vle16.v v26, (a1)
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; CHECK-NEXT: vle16.v v28, (a2)
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; CHECK-NEXT: vadd.vv v26, v26, v28
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; CHECK-NEXT: vse16.v v26, (a0)
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; CHECK-NEXT: ret
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%va = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pa
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%vb = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pb
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%vc = add <vscale x 8 x i16> %va, %vb
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store <vscale x 8 x i16> %vc, <vscale x 8 x i16> *%pc
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ret void
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}
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define void @vadd_vint16m4(<vscale x 16 x i16> *%pc, <vscale x 16 x i16> *%pa, <vscale x 16 x i16> *%pb) nounwind {
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; CHECK-LABEL: vadd_vint16m4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
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; CHECK-NEXT: vle16.v v28, (a1)
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; CHECK-NEXT: vle16.v v8, (a2)
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; CHECK-NEXT: vadd.vv v28, v28, v8
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; CHECK-NEXT: vse16.v v28, (a0)
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; CHECK-NEXT: ret
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%va = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pa
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%vb = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pb
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%vc = add <vscale x 16 x i16> %va, %vb
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store <vscale x 16 x i16> %vc, <vscale x 16 x i16> *%pc
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ret void
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}
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define void @vadd_vint16m8(<vscale x 32 x i16> *%pc, <vscale x 32 x i16> *%pa, <vscale x 32 x i16> *%pb) nounwind {
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; CHECK-LABEL: vadd_vint16m8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
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; CHECK-NEXT: vle16.v v8, (a1)
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; CHECK-NEXT: vle16.v v16, (a2)
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; CHECK-NEXT: vadd.vv v8, v8, v16
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; CHECK-NEXT: vse16.v v8, (a0)
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; CHECK-NEXT: ret
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%va = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pa
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%vb = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pb
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%vc = add <vscale x 32 x i16> %va, %vb
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store <vscale x 32 x i16> %vc, <vscale x 32 x i16> *%pc
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ret void
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}
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define void @vadd_vint16mf2(<vscale x 2 x i16> *%pc, <vscale x 2 x i16> *%pa, <vscale x 2 x i16> *%pb) nounwind {
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; CHECK-LABEL: vadd_vint16mf2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a3, zero, e16,mf2,ta,mu
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; CHECK-NEXT: vle16.v v25, (a1)
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; CHECK-NEXT: vle16.v v26, (a2)
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; CHECK-NEXT: vadd.vv v25, v25, v26
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; CHECK-NEXT: vse16.v v25, (a0)
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; CHECK-NEXT: ret
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%va = load <vscale x 2 x i16>, <vscale x 2 x i16>* %pa
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%vb = load <vscale x 2 x i16>, <vscale x 2 x i16>* %pb
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%vc = add <vscale x 2 x i16> %va, %vb
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store <vscale x 2 x i16> %vc, <vscale x 2 x i16> *%pc
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ret void
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}
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define void @vadd_vint16mf4(<vscale x 1 x i16> *%pc, <vscale x 1 x i16> *%pa, <vscale x 1 x i16> *%pb) nounwind {
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; CHECK-LABEL: vadd_vint16mf4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a3, zero, e16,mf4,ta,mu
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; CHECK-NEXT: vle16.v v25, (a1)
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; CHECK-NEXT: vle16.v v26, (a2)
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; CHECK-NEXT: vadd.vv v25, v25, v26
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; CHECK-NEXT: vse16.v v25, (a0)
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; CHECK-NEXT: ret
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%va = load <vscale x 1 x i16>, <vscale x 1 x i16>* %pa
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%vb = load <vscale x 1 x i16>, <vscale x 1 x i16>* %pb
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%vc = add <vscale x 1 x i16> %va, %vb
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store <vscale x 1 x i16> %vc, <vscale x 1 x i16> *%pc
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ret void
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}
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