276 lines
7.0 KiB
LLVM
276 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
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define i32 @fcmp_false(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_false:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: mv a0, zero
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_false:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: mv a0, zero
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; RV64IZFH-NEXT: ret
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%1 = fcmp false half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_oeq(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_oeq:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_oeq:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp oeq half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ogt(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ogt:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa1, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ogt:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa1, fa0
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; RV64IZFH-NEXT: ret
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%1 = fcmp ogt half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_oge(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_oge:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa1, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_oge:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa1, fa0
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; RV64IZFH-NEXT: ret
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%1 = fcmp oge half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_olt(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_olt:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_olt:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp olt half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ole(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ole:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ole:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp ole half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_one(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_one:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: flt.h a1, fa1, fa0
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; RV32IZFH-NEXT: or a0, a1, a0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_one:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: flt.h a1, fa1, fa0
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; RV64IZFH-NEXT: or a0, a1, a0
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; RV64IZFH-NEXT: ret
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%1 = fcmp one half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ord(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ord:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa1, fa1
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; RV32IZFH-NEXT: feq.h a1, fa0, fa0
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; RV32IZFH-NEXT: and a0, a1, a0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ord:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa1, fa1
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; RV64IZFH-NEXT: feq.h a1, fa0, fa0
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; RV64IZFH-NEXT: and a0, a1, a0
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; RV64IZFH-NEXT: ret
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%1 = fcmp ord half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ueq(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ueq:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: flt.h a1, fa1, fa0
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; RV32IZFH-NEXT: or a0, a1, a0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ueq:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: flt.h a1, fa1, fa0
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; RV64IZFH-NEXT: or a0, a1, a0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp ueq half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ugt(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ugt:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa0, fa1
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ugt:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa0, fa1
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp ugt half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_uge(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_uge:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_uge:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp uge half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ult(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ult:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa1, fa0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ult:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa1, fa0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp ult half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ule(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_ule:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa1, fa0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_ule:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa1, fa0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp ule half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_une(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_une:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_une:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp une half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_uno(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_uno:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa1, fa1
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; RV32IZFH-NEXT: feq.h a1, fa0, fa0
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; RV32IZFH-NEXT: and a0, a1, a0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_uno:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa1, fa1
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; RV64IZFH-NEXT: feq.h a1, fa0, fa0
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; RV64IZFH-NEXT: and a0, a1, a0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp uno half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_true(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fcmp_true:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi a0, zero, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fcmp_true:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi a0, zero, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp true half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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