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llvm-for-llvmta/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir

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# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE
--- |
; ModuleID = 'rlwinm_rldicl_to_andi.ll'
source_filename = "rlwinm_rldicl_to_andi.c"
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone
define signext i32 @testRLWINMSingleUseDef(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%shl.mask = and i32 %a, 1048575
%tobool = icmp eq i32 %shl.mask, 0
%cond = select i1 %tobool, i32 %a, i32 %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testRLWINMNoGPRUseZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%shl.mask = and i32 %a, 1048575
%tobool = icmp eq i32 %shl.mask, 0
%cond = select i1 %tobool, i32 %a, i32 %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testRLWINMNoGPRUseNonZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%shl.mask = and i32 %a, 1048575
%tobool = icmp eq i32 %shl.mask, 0
%cond = select i1 %tobool, i32 %a, i32 %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICLSingleUseDef(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shl.mask = and i64 %a, 4503599627370495
%tobool = icmp eq i64 %shl.mask, 0
%cond = select i1 %tobool, i64 %a, i64 %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICLNoGPRUseZero(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shl.mask = and i64 %a, 4503599627370495
%tobool = icmp eq i64 %shl.mask, 0
%cond = select i1 %tobool, i64 %a, i64 %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICLNoGPRUseNonZero(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shl.mask = and i64 %a, 4503599627370495
%tobool = icmp eq i64 %shl.mask, 0
%cond = select i1 %tobool, i64 %a, i64 %b
ret i64 %cond
}
attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"PIC Level", i32 2}
!2 = !{!"clang version 7.0.0 (trunk 322378)"}
...
---
name: testRLWINMSingleUseDef
# CHECK: testRLWINMSingleUseDef
# CHECK-LATE: testRLWINMSingleUseDef
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc = COPY $x4
%0:g8rc = COPY $x3
%2:gprc_and_gprc_nor0 = COPY %1.sub_32
%3:gprc = LI -11
%4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
; CHECK: LI 4055
; CHECK: ANDI_rec %3, 4055
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rlwinm.
%5:crrc = COPY killed $cr0
%6:gprc = ISEL %4, %2, %5.sub_eq
%7:g8rc = EXTSW_32_64 killed %6
$x3 = COPY %7
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testRLWINMNoGPRUseZero
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc = COPY $x4
%0:g8rc = COPY $x3
%2:gprc_and_gprc_nor0 = COPY %1.sub_32
%3:gprc_and_gprc_nor0 = LI 1
%4:gprc = RLWINM_rec %3, 21, 20, 31, implicit-def $cr0
; CHECK: LI 1
; CHECK: ANDI_rec %3, 0
; CHECK-LATE: li [[IMM:[0-9]+]], 1
; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
%5:crrc = COPY killed $cr0
%6:gprc = ISEL %3, %2, %5.sub_eq
%7:g8rc = EXTSW_32_64 killed %6
$x3 = COPY %7
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testRLWINMNoGPRUseNonZero
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc = COPY $x4
%0:g8rc = COPY $x3
%2:gprc_and_gprc_nor0 = COPY %1.sub_32
%3:gprc_and_gprc_nor0 = LI -11
%4:gprc = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
; CHECK: LI -11
; CHECK: ANDI_rec %3, 65525
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rlwinm.
%5:crrc = COPY killed $cr0
%6:gprc = ISEL %3, %2, %5.sub_eq
%7:g8rc = EXTSW_32_64 killed %6
$x3 = COPY %7
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testRLDICLSingleUseDef
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc_and_g8rc_nox0 = COPY $x4
%0:g8rc = LI8 -11
%2:g8rc_and_g8rc_nox0 = RLDICL_rec %0, 2, 49, implicit-def $cr0
; CHECK: LI8 32727
; CHECK: ANDI8_rec %0, 32727
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rldicl.
%3:crrc = COPY killed $cr0
%4:g8rc = ISEL8 %2, %1, %3.sub_eq
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testRLDICLNoGPRUseZero
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc_and_g8rc_nox0 = COPY $x4
%0:g8rc_and_g8rc_nox0 = LI8 1
%2:g8rc = RLDICL_rec %0, 32, 33, implicit-def $cr0
; CHECK: LI8 1
; CHECK: ANDI8_rec %0, 0
; CHECK-LATE: li [[IMM:[0-9]+]], 1
; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
%3:crrc = COPY killed $cr0
%4:g8rc = ISEL8 %0, %1, %3.sub_eq
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testRLDICLNoGPRUseNonZero
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc_and_g8rc_nox0 = COPY $x4
%0:g8rc_and_g8rc_nox0 = LI8 -11
%2:g8rc = RLDICL_rec %0, 2, 49, implicit-def $cr0
; CHECK: LI8 -11
; CHECK: ANDI8_rec %0, 65525
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rldicl.
%3:crrc = COPY killed $cr0
%4:g8rc = ISEL8 %0, %1, %3.sub_eq
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
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