139 lines
4.3 KiB
LLVM
139 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector divide instructions on Power10.
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; This includes the low order and extended versions of vector divide,
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; that operate on signed and unsigned words and doublewords.
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; This also includes 128 bit vector divide instructions.
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define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivud:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivud v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = udiv <2 x i64> %a, %b
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ret <2 x i64> %div
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}
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define <2 x i64> @test_vdivsd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivsd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivsd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = sdiv <2 x i64> %a, %b
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ret <2 x i64> %div
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}
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define <4 x i32> @test_vdivuw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivuw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = udiv <4 x i32> %a, %b
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ret <4 x i32> %div
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}
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define <4 x i32> @test_vdivsw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivsw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = sdiv <4 x i32> %a, %b
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ret <4 x i32> %div
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}
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; Test the vector divide extended intrinsics.
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declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32>, <4 x i32>)
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declare <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64>, <2 x i64>)
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define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivesw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivesw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = tail call <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %div
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}
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define <4 x i32> @test_vdiveuw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdiveuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiveuw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = tail call <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %div
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}
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define <1 x i128> @test_vdivsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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; CHECK-LABEL: test_vdivsq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vdivsq v2, v2, v3
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; CHECK-NEXT: blr
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%tmp = sdiv <1 x i128> %x, %y
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ret <1 x i128> %tmp
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}
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define <1 x i128> @test_vdivuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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; CHECK-LABEL: test_vdivuq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vdivuq v2, v2, v3
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; CHECK-NEXT: blr
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%tmp = udiv <1 x i128> %x, %y
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ret <1 x i128> %tmp
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}
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define <2 x i64> @test_vdivesd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivesd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivesd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = tail call <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %div
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}
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define <2 x i64> @test_vdiveud(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdiveud:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiveud v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = tail call <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %div
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}
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declare <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128>, <1 x i128>) nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128>, <1 x i128>) nounwind readnone
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define <1 x i128> @test_vdivesq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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; CHECK-LABEL: test_vdivesq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vdivesq v2, v2, v3
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; CHECK-NEXT: blr
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128> %x, <1 x i128> %y)
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ret <1 x i128> %tmp
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}
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define <1 x i128> @test_vdiveuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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; CHECK-LABEL: test_vdiveuq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vdiveuq v2, v2, v3
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; CHECK-NEXT: blr
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%tmp = call <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128> %x, <1 x i128> %y)
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ret <1 x i128> %tmp
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}
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