304 lines
10 KiB
LLVM
304 lines
10 KiB
LLVM
; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr7 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR
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; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 < %s | FileCheck %s -check-prefix=FIXPOINT
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Verify that the first two adds are independent regardless of how the inputs are
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; commuted. The destination registers are used as source registers for the third add.
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define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds1:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz float %x0, %x1
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%t1 = fadd reassoc nsz float %t0, %x2
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%t2 = fadd reassoc nsz float %t1, %x3
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ret float %t2
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}
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define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds2:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz float %x0, %x1
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%t1 = fadd reassoc nsz float %x2, %t0
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%t2 = fadd reassoc nsz float %t1, %x3
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ret float %t2
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}
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define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds3:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz float %x0, %x1
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%t1 = fadd reassoc nsz float %t0, %x2
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%t2 = fadd reassoc nsz float %x3, %t1
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ret float %t2
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}
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define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds4:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz float %x0, %x1
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%t1 = fadd reassoc nsz float %x2, %t0
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%t2 = fadd reassoc nsz float %x3, %t1
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ret float %t2
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}
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; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not
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; produced because that would cost more compile time.
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define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
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; CHECK-LABEL: reassociate_adds5:
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; CHECK: # %bb.0:
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; CHECK-DAG: fadds [[REG12:[0-9]+]], 5, 6
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; CHECK-DAG: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK-DAG: fadds [[REG11:[0-9]+]], 3, 4
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; CHECK-DAG: fadds [[REG13:[0-9]+]], [[REG12]], 7
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; CHECK-DAG: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
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; CHECK-DAG: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
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; CHECK: fadds 1, [[REG2]], 8
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz float %x0, %x1
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%t1 = fadd reassoc nsz float %t0, %x2
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%t2 = fadd reassoc nsz float %t1, %x3
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%t3 = fadd reassoc nsz float %t2, %x4
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%t4 = fadd reassoc nsz float %t3, %x5
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%t5 = fadd reassoc nsz float %t4, %x6
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%t6 = fadd reassoc nsz float %t5, %x7
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ret float %t6
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}
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; Verify that we reassociate vector instructions too.
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define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds1:
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; CHECK: # %bb.0:
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz <4 x float> %x0, %x1
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%t1 = fadd reassoc nsz <4 x float> %t0, %x2
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%t2 = fadd reassoc nsz <4 x float> %t1, %x3
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ret <4 x float> %t2
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}
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define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds2:
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; CHECK: # %bb.0:
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz <4 x float> %x0, %x1
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%t1 = fadd reassoc nsz <4 x float> %x2, %t0
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%t2 = fadd reassoc nsz <4 x float> %t1, %x3
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ret <4 x float> %t2
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}
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define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds3:
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; CHECK: # %bb.0:
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz <4 x float> %x0, %x1
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%t1 = fadd reassoc nsz <4 x float> %t0, %x2
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%t2 = fadd reassoc nsz <4 x float> %x3, %t1
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ret <4 x float> %t2
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}
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define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds4:
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; CHECK: # %bb.0:
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd reassoc nsz <4 x float> %x0, %x1
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%t1 = fadd reassoc nsz <4 x float> %x2, %t0
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%t2 = fadd reassoc nsz <4 x float> %x3, %t1
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ret <4 x float> %t2
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}
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define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) {
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%t0 = fdiv float %x0, %x1
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%t1 = fadd float %x2, %t0
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%t2 = fadd float %x3, %t1
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ret float %t2
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}
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define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
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%t0 = fdiv float %x0, %x1
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%t1 = fmul float %x2, %t0
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%t2 = fmul float %x3, %t1
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ret float %t2
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}
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define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {
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%t0 = fdiv double %x0, %x1
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%t1 = fadd double %x2, %t0
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%t2 = fadd double %x3, %t1
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ret double %t2
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}
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define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
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%t0 = fdiv double %x0, %x1
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%t1 = fmul double %x2, %t0
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%t2 = fmul double %x3, %t1
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ret double %t2
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}
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define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
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; FIXPOINT-LABEL: reassociate_mullw:
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; FIXPOINT: # %bb.0:
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; FIXPOINT: mullw [[REG0:[0-9]+]], 3, 4
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; FIXPOINT: mullw [[REG1:[0-9]+]], 5, 6
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; FIXPOINT: mullw 3, [[REG0]], [[REG1]]
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; FIXPOINT-NEXT: blr
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%t0 = mul i32 %x0, %x1
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%t1 = mul i32 %t0, %x2
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%t2 = mul i32 %t1, %x3
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ret i32 %t2
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}
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define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
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; FIXPOINT-LABEL: reassociate_mulld:
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; FIXPOINT: # %bb.0:
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; FIXPOINT: mulld [[REG0:[0-9]+]], 3, 4
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; FIXPOINT: mulld [[REG1:[0-9]+]], 5, 6
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; FIXPOINT: mulld 3, [[REG0]], [[REG1]]
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; FIXPOINT-NEXT: blr
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%t0 = mul i64 %x0, %x1
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%t1 = mul i64 %t0, %x2
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%t2 = mul i64 %t1, %x3
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ret i64 %t2
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}
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define double @reassociate_mamaa_double(double %0, double %1, double %2, double %3, double %4, double %5) {
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; CHECK-LABEL: reassociate_mamaa_double:
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; CHECK: # %bb.0:
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; CHECK-PWR-DAG: xsmaddadp 1, 6, 5
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; CHECK-PWR-DAG: xsmaddadp 2, 4, 3
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; CHECK-PWR: xsadddp 1, 2, 1
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; CHECK-NEXT: blr
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%7 = fmul reassoc nsz double %3, %2
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%8 = fmul reassoc nsz double %5, %4
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%9 = fadd reassoc nsz double %1, %0
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%10 = fadd reassoc nsz double %9, %7
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%11 = fadd reassoc nsz double %10, %8
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ret double %11
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}
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define float @reassociate_mamaa_float(float %0, float %1, float %2, float %3, float %4, float %5) {
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; CHECK-LABEL: reassociate_mamaa_float:
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; CHECK: # %bb.0:
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; CHECK-DAG: fmadds [[REG0:[0-9]+]], 4, 3, 2
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; CHECK-DAG: fmadds [[REG1:[0-9]+]], 6, 5, 1
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%7 = fmul reassoc nsz float %3, %2
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%8 = fmul reassoc nsz float %5, %4
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%9 = fadd reassoc nsz float %1, %0
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%10 = fadd reassoc nsz float %9, %7
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%11 = fadd reassoc nsz float %10, %8
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ret float %11
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}
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define <4 x float> @reassociate_mamaa_vec(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3, <4 x float> %4, <4 x float> %5) {
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; CHECK-LABEL: reassociate_mamaa_vec:
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; CHECK: # %bb.0:
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; CHECK-PWR-DAG: xvmaddasp [[REG0:[0-9]+]], 39, 38
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; CHECK-PWR-DAG: xvmaddasp [[REG1:[0-9]+]], 37, 36
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; CHECK-PWR: xvaddsp 34, [[REG1]], [[REG0]]
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; CHECK-NEXT: blr
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%7 = fmul reassoc nsz <4 x float> %3, %2
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%8 = fmul reassoc nsz <4 x float> %5, %4
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%9 = fadd reassoc nsz <4 x float> %1, %0
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%10 = fadd reassoc nsz <4 x float> %9, %7
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%11 = fadd reassoc nsz <4 x float> %10, %8
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ret <4 x float> %11
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}
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define double @reassociate_mamama_double(double %0, double %1, double %2, double %3, double %4, double %5, double %6, double %7, double %8) {
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; CHECK-LABEL: reassociate_mamama_double:
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; CHECK: # %bb.0:
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; CHECK-PWR: xsmaddadp 7, 2, 1
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; CHECK-PWR-DAG: xsmuldp [[REG0:[0-9]+]], 4, 3
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; CHECK-PWR-DAG: xsmaddadp 7, 6, 5
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; CHECK-PWR-DAG: xsmaddadp [[REG0]], 9, 8
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; CHECK-PWR: xsadddp 1, 7, [[REG0]]
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; CHECK-NEXT: blr
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%10 = fmul reassoc nsz double %1, %0
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%11 = fmul reassoc nsz double %3, %2
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%12 = fmul reassoc nsz double %5, %4
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%13 = fmul reassoc nsz double %8, %7
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%14 = fadd reassoc nsz double %11, %10
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%15 = fadd reassoc nsz double %14, %6
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%16 = fadd reassoc nsz double %15, %12
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%17 = fadd reassoc nsz double %16, %13
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ret double %17
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}
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define dso_local float @reassociate_mamama_8(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8,
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float %9, float %10, float %11, float %12, float %13, float %14, float %15, float %16) {
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; CHECK-LABEL: reassociate_mamama_8:
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; CHECK: # %bb.0:
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; CHECK-DAG: fmadds [[REG0:[0-9]+]], 3, 2, 1
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; CHECK-DAG: fmuls [[REG1:[0-9]+]], 5, 4
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; CHECK-DAG: fmadds [[REG2:[0-9]+]], 7, 6, [[REG0]]
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; CHECK-DAG: fmadds [[REG3:[0-9]+]], 9, 8, [[REG1]]
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;
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; CHECK-DAG: fmadds [[REG4:[0-9]+]], 13, 12, [[REG3]]
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; CHECK-DAG: fmadds [[REG5:[0-9]+]], 11, 10, [[REG2]]
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;
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; CHECK-DAG: fmadds [[REG6:[0-9]+]], 3, 2, [[REG4]]
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; CHECK-DAG: fmadds [[REG7:[0-9]+]], 5, 4, [[REG5]]
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; CHECK: fadds 1, [[REG7]], [[REG6]]
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; CHECK-NEXT: blr
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%18 = fmul reassoc nsz float %2, %1
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%19 = fadd reassoc nsz float %18, %0
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%20 = fmul reassoc nsz float %4, %3
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%21 = fadd reassoc nsz float %19, %20
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%22 = fmul reassoc nsz float %6, %5
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%23 = fadd reassoc nsz float %21, %22
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%24 = fmul reassoc nsz float %8, %7
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%25 = fadd reassoc nsz float %23, %24
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%26 = fmul reassoc nsz float %10, %9
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%27 = fadd reassoc nsz float %25, %26
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%28 = fmul reassoc nsz float %12, %11
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%29 = fadd reassoc nsz float %27, %28
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%30 = fmul reassoc nsz float %14, %13
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%31 = fadd reassoc nsz float %29, %30
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%32 = fmul reassoc nsz float %16, %15
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%33 = fadd reassoc nsz float %31, %32
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ret float %33
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}
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