73 lines
1.7 KiB
LLVM
73 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -fp-contract=fast | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -fp-contract=fast | FileCheck %s
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;; These tests should run for all targets
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;;===-- Basic instruction selection tests ---------------------------------===;;
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;;; f64
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define double @fadd_f64(double %a, double %b) {
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; CHECK: add.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
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; CHECK: ret
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%ret = fadd double %a, %b
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ret double %ret
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}
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define double @fsub_f64(double %a, double %b) {
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; CHECK: sub.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
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; CHECK: ret
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%ret = fsub double %a, %b
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ret double %ret
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}
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define double @fmul_f64(double %a, double %b) {
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; CHECK: mul.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
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; CHECK: ret
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%ret = fmul double %a, %b
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ret double %ret
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}
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define double @fdiv_f64(double %a, double %b) {
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; CHECK: div.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
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; CHECK: ret
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%ret = fdiv double %a, %b
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ret double %ret
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}
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;; PTX does not have a floating-point rem instruction
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;;; f32
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define float @fadd_f32(float %a, float %b) {
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; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
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; CHECK: ret
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%ret = fadd float %a, %b
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ret float %ret
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}
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define float @fsub_f32(float %a, float %b) {
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; CHECK: sub.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
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; CHECK: ret
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%ret = fsub float %a, %b
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ret float %ret
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}
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define float @fmul_f32(float %a, float %b) {
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; CHECK: mul.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
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; CHECK: ret
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%ret = fmul float %a, %b
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ret float %ret
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}
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define float @fdiv_f32(float %a, float %b) {
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; CHECK: div.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
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; CHECK: ret
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%ret = fdiv float %a, %b
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ret float %ret
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}
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;; PTX does not have a floating-point rem instruction
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