357 lines
9.4 KiB
LLVM
357 lines
9.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
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define float @i64tof32(i64 signext %a) {
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; MIPS32-LABEL: i64tof32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -24
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; MIPS32-NEXT: .cfi_def_cfa_offset 24
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; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: .cfi_offset 31, -4
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; MIPS32-NEXT: jal __floatdisf
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 24
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i64 %a to float
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ret float %conv
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}
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define float @i32tof32(i32 signext %a) {
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; MIPS32-LABEL: i32tof32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: mtc1 $4, $f0
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; MIPS32-NEXT: cvt.s.w $f0, $f0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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define float @i16tof32(i16 signext %a) {
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; MIPS32-LABEL: i16tof32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 16
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; MIPS32-NEXT: sra $1, $1, 16
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; MIPS32-NEXT: mtc1 $1, $f0
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; MIPS32-NEXT: cvt.s.w $f0, $f0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i16 %a to float
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ret float %conv
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}
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define float @i8tof32(i8 signext %a) {
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; MIPS32-LABEL: i8tof32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 24
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; MIPS32-NEXT: sra $1, $1, 24
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; MIPS32-NEXT: mtc1 $1, $f0
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; MIPS32-NEXT: cvt.s.w $f0, $f0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i8 %a to float
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ret float %conv
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}
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define double @i64tof64(i64 signext %a) {
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; MIPS32-LABEL: i64tof64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -24
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; MIPS32-NEXT: .cfi_def_cfa_offset 24
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; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: .cfi_offset 31, -4
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; MIPS32-NEXT: jal __floatdidf
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 24
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i64 %a to double
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ret double %conv
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}
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define double @i32tof64(i32 signext %a) {
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; MIPS32-LABEL: i32tof64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: mtc1 $4, $f0
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; MIPS32-NEXT: cvt.d.w $f0, $f0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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define double @i16tof64(i16 signext %a) {
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; MIPS32-LABEL: i16tof64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 16
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; MIPS32-NEXT: sra $1, $1, 16
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; MIPS32-NEXT: mtc1 $1, $f0
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; MIPS32-NEXT: cvt.d.w $f0, $f0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i16 %a to double
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ret double %conv
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}
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define double @i8tof64(i8 signext %a) {
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; MIPS32-LABEL: i8tof64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 24
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; MIPS32-NEXT: sra $1, $1, 24
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; MIPS32-NEXT: mtc1 $1, $f0
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; MIPS32-NEXT: cvt.d.w $f0, $f0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sitofp i8 %a to double
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ret double %conv
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}
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define float @u64tof32(i64 zeroext %a) {
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; MIPS32-LABEL: u64tof32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -24
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; MIPS32-NEXT: .cfi_def_cfa_offset 24
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; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: .cfi_offset 31, -4
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; MIPS32-NEXT: jal __floatundisf
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 24
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = uitofp i64 %a to float
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ret float %conv
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}
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define float @u32tof32(i32 zeroext %a) {
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; FP32-LABEL: u32tof32:
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; FP32: # %bb.0: # %entry
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; FP32-NEXT: lui $1, 17200
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; FP32-NEXT: mtc1 $4, $f0
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; FP32-NEXT: mtc1 $1, $f1
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: ori $1, $zero, 0
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; FP32-NEXT: mtc1 $1, $f2
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; FP32-NEXT: mtc1 $2, $f3
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; FP32-NEXT: sub.d $f0, $f0, $f2
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; FP32-NEXT: cvt.s.d $f0, $f0
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; FP32-NEXT: jr $ra
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; FP32-NEXT: nop
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;
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; FP64-LABEL: u32tof32:
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; FP64: # %bb.0: # %entry
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; FP64-NEXT: lui $1, 17200
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; FP64-NEXT: mtc1 $4, $f0
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; FP64-NEXT: mthc1 $1, $f0
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: ori $1, $zero, 0
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; FP64-NEXT: mtc1 $1, $f1
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; FP64-NEXT: mthc1 $2, $f1
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; FP64-NEXT: sub.d $f0, $f0, $f1
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; FP64-NEXT: cvt.s.d $f0, $f0
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; FP64-NEXT: jr $ra
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; FP64-NEXT: nop
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entry:
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%conv = uitofp i32 %a to float
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ret float %conv
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}
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define float @u16tof32(i16 zeroext %a) {
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; FP32-LABEL: u16tof32:
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; FP32: # %bb.0: # %entry
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; FP32-NEXT: andi $1, $4, 65535
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: mtc1 $1, $f0
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; FP32-NEXT: mtc1 $2, $f1
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: ori $1, $zero, 0
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; FP32-NEXT: mtc1 $1, $f2
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; FP32-NEXT: mtc1 $2, $f3
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; FP32-NEXT: sub.d $f0, $f0, $f2
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; FP32-NEXT: cvt.s.d $f0, $f0
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; FP32-NEXT: jr $ra
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; FP32-NEXT: nop
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;
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; FP64-LABEL: u16tof32:
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; FP64: # %bb.0: # %entry
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; FP64-NEXT: andi $1, $4, 65535
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: mtc1 $1, $f0
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; FP64-NEXT: mthc1 $2, $f0
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: ori $1, $zero, 0
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; FP64-NEXT: mtc1 $1, $f1
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; FP64-NEXT: mthc1 $2, $f1
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; FP64-NEXT: sub.d $f0, $f0, $f1
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; FP64-NEXT: cvt.s.d $f0, $f0
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; FP64-NEXT: jr $ra
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; FP64-NEXT: nop
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entry:
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%conv = uitofp i16 %a to float
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ret float %conv
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}
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define float @u8tof32(i8 zeroext %a) {
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; FP32-LABEL: u8tof32:
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; FP32: # %bb.0: # %entry
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; FP32-NEXT: andi $1, $4, 255
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: mtc1 $1, $f0
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; FP32-NEXT: mtc1 $2, $f1
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: ori $1, $zero, 0
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; FP32-NEXT: mtc1 $1, $f2
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; FP32-NEXT: mtc1 $2, $f3
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; FP32-NEXT: sub.d $f0, $f0, $f2
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; FP32-NEXT: cvt.s.d $f0, $f0
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; FP32-NEXT: jr $ra
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; FP32-NEXT: nop
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;
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; FP64-LABEL: u8tof32:
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; FP64: # %bb.0: # %entry
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; FP64-NEXT: andi $1, $4, 255
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: mtc1 $1, $f0
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; FP64-NEXT: mthc1 $2, $f0
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: ori $1, $zero, 0
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; FP64-NEXT: mtc1 $1, $f1
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; FP64-NEXT: mthc1 $2, $f1
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; FP64-NEXT: sub.d $f0, $f0, $f1
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; FP64-NEXT: cvt.s.d $f0, $f0
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; FP64-NEXT: jr $ra
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; FP64-NEXT: nop
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entry:
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%conv = uitofp i8 %a to float
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ret float %conv
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}
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define double @u64tof64(i64 zeroext %a) {
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; MIPS32-LABEL: u64tof64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -24
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; MIPS32-NEXT: .cfi_def_cfa_offset 24
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; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: .cfi_offset 31, -4
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; MIPS32-NEXT: jal __floatundidf
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 24
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = uitofp i64 %a to double
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ret double %conv
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}
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define double @u32tof64(i32 zeroext %a) {
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; FP32-LABEL: u32tof64:
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; FP32: # %bb.0: # %entry
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; FP32-NEXT: lui $1, 17200
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; FP32-NEXT: mtc1 $4, $f0
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; FP32-NEXT: mtc1 $1, $f1
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: ori $1, $zero, 0
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; FP32-NEXT: mtc1 $1, $f2
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; FP32-NEXT: mtc1 $2, $f3
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; FP32-NEXT: sub.d $f0, $f0, $f2
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; FP32-NEXT: jr $ra
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; FP32-NEXT: nop
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;
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; FP64-LABEL: u32tof64:
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; FP64: # %bb.0: # %entry
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; FP64-NEXT: lui $1, 17200
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; FP64-NEXT: mtc1 $4, $f0
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; FP64-NEXT: mthc1 $1, $f0
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: ori $1, $zero, 0
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; FP64-NEXT: mtc1 $1, $f1
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; FP64-NEXT: mthc1 $2, $f1
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; FP64-NEXT: sub.d $f0, $f0, $f1
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; FP64-NEXT: jr $ra
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; FP64-NEXT: nop
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entry:
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%conv = uitofp i32 %a to double
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ret double %conv
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}
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define double @u16tof64(i16 zeroext %a) {
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; FP32-LABEL: u16tof64:
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; FP32: # %bb.0: # %entry
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; FP32-NEXT: andi $1, $4, 65535
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: mtc1 $1, $f0
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; FP32-NEXT: mtc1 $2, $f1
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: ori $1, $zero, 0
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; FP32-NEXT: mtc1 $1, $f2
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; FP32-NEXT: mtc1 $2, $f3
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; FP32-NEXT: sub.d $f0, $f0, $f2
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; FP32-NEXT: jr $ra
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; FP32-NEXT: nop
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;
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; FP64-LABEL: u16tof64:
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; FP64: # %bb.0: # %entry
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; FP64-NEXT: andi $1, $4, 65535
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: mtc1 $1, $f0
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; FP64-NEXT: mthc1 $2, $f0
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: ori $1, $zero, 0
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; FP64-NEXT: mtc1 $1, $f1
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; FP64-NEXT: mthc1 $2, $f1
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; FP64-NEXT: sub.d $f0, $f0, $f1
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; FP64-NEXT: jr $ra
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; FP64-NEXT: nop
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entry:
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%conv = uitofp i16 %a to double
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ret double %conv
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}
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define double @u8tof64(i8 zeroext %a) {
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; FP32-LABEL: u8tof64:
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; FP32: # %bb.0: # %entry
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; FP32-NEXT: andi $1, $4, 255
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: mtc1 $1, $f0
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; FP32-NEXT: mtc1 $2, $f1
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; FP32-NEXT: lui $2, 17200
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; FP32-NEXT: ori $1, $zero, 0
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; FP32-NEXT: mtc1 $1, $f2
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; FP32-NEXT: mtc1 $2, $f3
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; FP32-NEXT: sub.d $f0, $f0, $f2
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; FP32-NEXT: jr $ra
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; FP32-NEXT: nop
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;
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; FP64-LABEL: u8tof64:
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; FP64: # %bb.0: # %entry
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; FP64-NEXT: andi $1, $4, 255
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: mtc1 $1, $f0
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; FP64-NEXT: mthc1 $2, $f0
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; FP64-NEXT: lui $2, 17200
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; FP64-NEXT: ori $1, $zero, 0
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; FP64-NEXT: mtc1 $1, $f1
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; FP64-NEXT: mthc1 $2, $f1
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; FP64-NEXT: sub.d $f0, $f0, $f1
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; FP64-NEXT: jr $ra
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; FP64-NEXT: nop
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entry:
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%conv = uitofp i8 %a to double
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ret double %conv
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}
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