128 lines
4.5 KiB
LLVM
128 lines
4.5 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s
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; REQUIRES: asserts
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; This file used to fail with an "UNREACHABLE executed!" in Post-RA pseudo
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; instruction expansion pass due to a bug in the TwoAddressInstructionPass we
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; were not handling sub register indexes when rewriting tied operands.
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target triple = "hexagon"
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%0 = type { i8, i8, %1, i32, i32, %7, i8, i8, %8, i8, i32, i16, i16, [2500 x i8], i16, i16, i16, i8*, [1024 x i8], i32, i32, i32, i32, i32, i8 }
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%1 = type { i8, %2, i8, i8, i32 }
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%2 = type { %3 }
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%3 = type { i8, [256 x i8], %4, i8, i16, i32 }
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%4 = type { %5 }
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%5 = type { %6 }
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%6 = type { [2 x i64] }
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%7 = type { i32, i8 }
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%8 = type { %7, i32, i32, %1 }
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%9 = type { %10, i8* }
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%10 = type { i16, i16, i32 }
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%11 = type { i8, i32 }
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@g0 = external hidden global [2 x %0], align 8
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@g1 = external hidden constant %9, align 4
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@g2 = external hidden constant %9, align 4
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@g3 = external hidden constant %9, align 4
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@g4 = external hidden constant %9, align 4
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; Function Attrs: optsize
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declare void @f0(%9*, i32, i32, i32) #0
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; Function Attrs: nounwind optsize ssp
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define hidden fastcc void @f1(i64 %a0, i8 zeroext %a1, i8 zeroext %a2) #1 {
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b0:
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%v0 = alloca %11, align 4
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%v1 = icmp ne i8 %a1, 0
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%v2 = trunc i64 %a0 to i32
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br i1 %v1, label %b1, label %b4
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b1: ; preds = %b0
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call void @f0(%9* @g1, i32 %v2, i32 0, i32 0) #2
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%v3 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 %v2, i32 7
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store i8 1, i8* %v3, align 1
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%v4 = icmp eq i8 %a2, 0
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br i1 %v4, label %b4, label %b2
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b2: ; preds = %b1
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%v5 = getelementptr inbounds %11, %11* %v0, i32 0, i32 0
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store i8 0, i8* %v5, align 4
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%v6 = getelementptr inbounds %11, %11* %v0, i32 0, i32 1
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store i32 0, i32* %v6, align 4
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%v7 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 %v2, i32 3
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%v8 = load i32, i32* %v7, align 8
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%v9 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 %v2, i32 4
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%v10 = load i32, i32* %v9, align 4
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%v11 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 %v2, i32 19
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%v12 = load i32, i32* %v11, align 4
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%v13 = call zeroext i8 @f2(i64 %a0, i32 %v8, i32 %v10, i32 %v12, i8 zeroext 0, %11* %v0) #2
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%v14 = icmp eq i8 %v13, 0
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br i1 %v14, label %b4, label %b3
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b3: ; preds = %b2
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%v15 = zext i8 %v13 to i32
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call void @f0(%9* @g2, i32 %v15, i32 %v2, i32 0) #2
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br label %b4
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b4: ; preds = %b3, %b2, %b1, %b0
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%v16 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 %v2, i32 1
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%v17 = load i8, i8* %v16, align 1
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%v18 = zext i8 %v17 to i32
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switch i32 %v18, label %b14 [
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i32 2, label %b11
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i32 1, label %b5
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i32 4, label %b8
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i32 3, label %b11
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]
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b5: ; preds = %b4
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call void @f0(%9* @g3, i32 %v2, i32 0, i32 0) #2
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br i1 %v1, label %b7, label %b6
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b6: ; preds = %b5
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call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0
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br label %b14
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b7: ; preds = %b5
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call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0
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br label %b14
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b8: ; preds = %b4
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call void @f0(%9* @g4, i32 %v2, i32 0, i32 0) #2
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%v19 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 %v2, i32 6
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store i8 1, i8* %v19, align 8
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br i1 %v1, label %b10, label %b9
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b9: ; preds = %b8
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call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0
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br label %b14
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b10: ; preds = %b8
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call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0
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br label %b14
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b11: ; preds = %b4, %b4
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br i1 %v1, label %b13, label %b12
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b12: ; preds = %b11
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call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0
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br label %b14
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b13: ; preds = %b11
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call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0
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br label %b14
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b14: ; preds = %b13, %b12, %b10, %b9, %b7, %b6, %b4
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ret void
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}
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; Function Attrs: optsize
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declare zeroext i8 @f2(i64, i32, i32, i32, i8 zeroext, %11*) #0
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; Function Attrs: nounwind optsize ssp
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declare hidden fastcc void @f3(i64, i8 zeroext, i8 zeroext, i32) #1
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attributes #0 = { optsize }
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attributes #1 = { nounwind optsize ssp }
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attributes #2 = { nounwind optsize }
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