448 lines
18 KiB
LLVM
448 lines
18 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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@c = external global <32 x i32>
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@d = external global <16 x i32>
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; CHECK-LABEL: test1:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.b,r{{[0-9]+}}.b)
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define void @test1(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vtmpyb.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test2:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)
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define void @test2(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vtmpybus.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test3:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)
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define void @test3(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vtmpyhb.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test4:
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; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.b)
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define void @test4(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhb.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test5:
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; CHECK: v{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)
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define void @test5(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpyub.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test6:
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; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)
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define void @test6(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybus.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test7:
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; CHECK: v{{[0-9]+}}.h += vdmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)
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define void @test7(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test8:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)
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define void @test8(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test9:
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; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.uh):sat
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define void @test9(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsusat.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test10:
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; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.uh,#1):sat
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define void @test10(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsuisat.acc(<16 x i32> %0, <32 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test11:
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; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.h):sat
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define void @test11(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhisat.acc(<16 x i32> %0, <32 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test12:
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; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat
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define void @test12(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsat.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test13:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)
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define void @test13(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vdmpyhb.dv.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test14:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)
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define void @test14(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test15:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpa(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)
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define void @test15(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test16:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpa(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)
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define void @test16(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test17:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat
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define void @test17(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test18:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vmpy(v{{[0-9]+}}.uh,r{{[0-9]+}}.uh)
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define void @test18(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuh.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test19:
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; CHECK: v{{[0-9]+}}.w += vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.b)
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define void @test19(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test20:
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; CHECK: v{{[0-9]+}}.w += vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.h)
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define void @test20(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test21:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vdsad(v{{[0-9]+}}:{{[0-9]+}}.uh,r{{[0-9]+}}.uh)
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define void @test21(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vdsaduh.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test22:
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; CHECK: v{{[0-9]+}}.h += vmpyi(v{{[0-9]+}}.h,r{{[0-9]+}}.b)
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define void @test22(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyihb.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test23:
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; CHECK: v{{[0-9]+}}.w += vasl(v{{[0-9]+}}.w,r{{[0-9]+}})
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define void @test23(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test24:
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; CHECK: v{{[0-9]+}}.w += vasr(v{{[0-9]+}}.w,r{{[0-9]+}})
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define void @test24(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test25:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh += vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)
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define void @test25(<16 x i32> %a, i32 %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test26:
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; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat
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define void @test26(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test27:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.b)
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define void @test27(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpybusv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test28:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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define void @test28(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpybv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test29:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.uh)
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define void @test29(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhus.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test30:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test30(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* @c, align 128
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <32 x i32> %1, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test31:
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; CHECK: v{{[0-9]+}}.w += vmpyie(v{{[0-9]+}}.w,v{{[0-9]+}}.h)
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define void @test31(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewh.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test32:
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; CHECK: v{{[0-9]+}}.w += vmpyie(v{{[0-9]+}}.w,v{{[0-9]+}}.uh)
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define void @test32(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* @d, align 64
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %1, <16 x i32>* @d, align 64
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ret void
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}
|
|
|
|
; CHECK-LABEL: test33:
|
|
; CHECK: v{{[0-9]+}}.h += vmpyi(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
|
|
define void @test33(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @d, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyih.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <16 x i32> %1, <16 x i32>* @d, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test34:
|
|
; CHECK: v{{[0-9]+}}.w += vmpyo(v{{[0-9]+}}.w,v{{[0-9]+}}.h):<<1:rnd:sat:shift
|
|
define void @test34(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @d, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyowh.rnd.sacc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <16 x i32> %1, <16 x i32>* @d, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test35:
|
|
; CHECK: v{{[0-9]+}}.w += vmpyo(v{{[0-9]+}}.w,v{{[0-9]+}}.h):<<1:sat:shift
|
|
define void @test35(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @d, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyowh.sacc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <16 x i32> %1, <16 x i32>* @d, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test36:
|
|
; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh += vmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
|
|
define void @test36(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <32 x i32>, <32 x i32>* @c, align 128
|
|
%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <32 x i32> %1, <32 x i32>* @c, align 128
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test37:
|
|
; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vmpy(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
|
|
define void @test37(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <32 x i32>, <32 x i32>* @c, align 128
|
|
%1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <32 x i32> %1, <32 x i32>* @c, align 128
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test38:
|
|
; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.b)
|
|
define void @test38(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @d, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybusv.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <16 x i32> %1, <16 x i32>* @d, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test39:
|
|
; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
|
|
define void @test39(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @d, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybv.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <16 x i32> %1, <16 x i32>* @d, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test40:
|
|
; CHECK: v{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
|
|
define void @test40(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @d, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpyubv.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
|
|
store <16 x i32> %1, <16 x i32>* @d, align 64
|
|
ret void
|
|
}
|
|
|
|
declare <32 x i32> @llvm.hexagon.V6.vtmpyb.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vtmpybus.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vtmpyhb.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpyhb.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vrmpyub.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vrmpybus.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpyhsusat.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpyhsuisat.acc(<16 x i32>, <32 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpyhisat.acc(<16 x i32>, <32 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpyhsat.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vdmpyhb.dv.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyuh.acc(<32 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vdsaduh.acc(<32 x i32>, <32 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyihb.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyub.acc(<32 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpybusv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpybv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyhus.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyhv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyiewh.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyih.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyowh.rnd.sacc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmpyowh.sacc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyubv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vmpyuhv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vrmpybusv.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vrmpybv.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vrmpyubv.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
|
|
|
|
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx60,+hvx-length64b" }
|