llvm-for-llvmta/test/CodeGen/Hexagon/cext-unnamed-global.mir

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# RUN: llc -march=hexagon -run-pass=hexagon-cext-opt %s -o - | FileCheck %s
# Check that this test doesn't crash.
# CHECK: %0:intregs = A2_tfrsi @0
--- |
target triple = "hexagon"
@0 = external global [0 x i8]
@1 = external constant [2 x i64]
define void @f0() #0 {
b0:
tail call fastcc void @f1(float* inttoptr (i64 add (i64 ptrtoint ([0 x i8]* @0 to i64), i64 128) to float*), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @1, i32 0, i32 0))
ret void
}
declare fastcc void @f1(float* nocapture readonly, i64* nocapture readonly) #1
attributes #0 = { alwaysinline nounwind "target-cpu"="hexagonv60" }
attributes #1 = { noinline norecurse nounwind "target-cpu"="hexagonv60" }
...
---
name: f0
tracksRegLiveness: true
body: |
bb.0:
%0:intregs = A2_tfrsi @0
%1:intregs = A2_tfrsi 0
%2:doubleregs = REG_SEQUENCE %0, %subreg.isub_lo, %1, %subreg.isub_hi
%3:doubleregs = CONST64 128
%4:doubleregs = A2_addp %2, %3
%5:intregs = A2_tfrsi @1
$r0 = COPY %4.isub_lo
$r1 = COPY %5
PS_tailcall_i @f1, hexagoncsr, implicit $r0, implicit $r1
...