llvm-for-llvmta/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_br() { ret void }
...
---
name: test_br
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
; CHECK-LABEL: name: test_br
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: t2TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, $cpsr
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
successors: %bb.2(0x80000000)
G_BR %bb.2
bb.2:
tBX_RET 14, $noreg
...