llvm-for-llvmta/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir

33 lines
1.4 KiB
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=regallocfast -o - %s | FileCheck %s
---
name: bar
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: bar
; CHECK: liveins: $vgpr0
; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
; CHECK: SI_SPILL_S64_SAVE $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
; CHECK: $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load 8 from %stack.0, align 4, addrspace 5)
; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $sgpr4_sgpr5, implicit $exec
; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed renamable $vcc
%0:vgpr_32 = COPY $vgpr0
V_CMP_NE_U32_e32 0, %0, implicit-def $vcc, implicit $exec
%3:sreg_64_xexec = COPY $vcc
%1:sreg_64_xexec = COPY $vcc
%2:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, 3, %1, implicit $exec
$vgpr0 = COPY %2
S_ENDPGM 0, implicit $vgpr0, implicit %3
...