135 lines
5.9 KiB
LLVM
135 lines
5.9 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}v_fsub_f32:
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define amdgpu_kernel void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in, align 4
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%b = load float, float addrspace(1)* %b_ptr, align 4
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%result = fsub float %a, %b
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_fsub_f32:
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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define amdgpu_kernel void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) {
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%sub = fsub float %a, %b
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store float %sub, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fsub_v2f32:
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; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
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; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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define amdgpu_kernel void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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%sub = fsub <2 x float> %a, %b
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store <2 x float> %sub, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_fsub_v4f32:
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define amdgpu_kernel void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16
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%b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16
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%result = fsub <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}s_fsub_v4f32:
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: s_endpgm
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define amdgpu_kernel void @s_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) {
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%result = fsub <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}v_fneg_fsub_f32:
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; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; SI: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]
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define amdgpu_kernel void @v_fneg_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in, align 4
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%b = load float, float addrspace(1)* %b_ptr, align 4
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%result = fsub float %a, %b
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%neg.result = fsub float -0.0, %result
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store float %neg.result, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_f32:
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; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; SI-NOT: xor
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define amdgpu_kernel void @v_fneg_fsub_nsz_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in, align 4
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%b = load float, float addrspace(1)* %b_ptr, align 4
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%result = fsub nsz float %a, %b
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%neg.result = fsub float -0.0, %result
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store float %neg.result, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_attribute_f32:
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; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; SI-NOT: xor
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define amdgpu_kernel void @v_fneg_fsub_nsz_attribute_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in, align 4
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%b = load float, float addrspace(1)* %b_ptr, align 4
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%result = fsub float %a, %b
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%neg.result = fsub float -0.0, %result
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store float %neg.result, float addrspace(1)* %out, align 4
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ret void
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}
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; For some reason the attribute has a string "true" or "false", so
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; make sure it is disabled and the fneg is not folded if it is not
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; "true".
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; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_false_attribute_f32:
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; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; SI: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]
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define amdgpu_kernel void @v_fneg_fsub_nsz_false_attribute_f32(float addrspace(1)* %out, float addrspace(1)* %in) #1 {
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in, align 4
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%b = load float, float addrspace(1)* %b_ptr, align 4
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%result = fsub float %a, %b
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%neg.result = fsub float -0.0, %result
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store float %neg.result, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_fsub_0_nsz_attribute_f32:
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; SI-NOT: v_sub
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define amdgpu_kernel void @v_fsub_0_nsz_attribute_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%a = load float, float addrspace(1)* %in, align 4
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%result = fsub float %a, 0.0
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
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attributes #1 = { nounwind "no-signed-zeros-fp-math"="false" }
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