162 lines
5.7 KiB
LLVM
162 lines
5.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; WHILERW
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;
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define <vscale x 16 x i1> @whilerw_i8(i8* %a, i8* %b) {
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; CHECK-LABEL: whilerw_i8:
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; CHECK: whilerw p0.b, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilerw.b.nx16i1(i8* %a, i8* %b)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 8 x i1> @whilerw_i16(i16* %a, i16* %b) {
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; CHECK-LABEL: whilerw_i16:
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; CHECK: whilerw p0.h, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1(i16* %a, i16* %b)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 4 x i1> @whilerw_i32(i32* %a, i32* %b) {
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; CHECK-LABEL: whilerw_i32:
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; CHECK: whilerw p0.s, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1(i32* %a, i32* %b)
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ret <vscale x 4 x i1> %out
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}
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define <vscale x 2 x i1> @whilerw_i64(i64* %a, i64* %b) {
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; CHECK-LABEL: whilerw_i64:
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; CHECK: whilerw p0.d, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1(i64* %a, i64* %b)
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ret <vscale x 2 x i1> %out
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}
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define <vscale x 8 x i1> @whilerw_bfloat(bfloat* %a, bfloat* %b) {
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; CHECK-LABEL: whilerw_bfloat:
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; CHECK: whilerw p0.h, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 8 x i1> @whilerw_half(half* %a, half* %b) {
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; CHECK-LABEL: whilerw_half:
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; CHECK: whilerw p0.h, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.f16.f16(half* %a, half* %b)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 4 x i1> @whilerw_float(float* %a, float* %b) {
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; CHECK-LABEL: whilerw_float:
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; CHECK: whilerw p0.s, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1.f32.f32(float* %a, float* %b)
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ret <vscale x 4 x i1> %out
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}
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define <vscale x 2 x i1> @whilerw_double(double* %a, double* %b) {
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; CHECK-LABEL: whilerw_double:
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; CHECK: whilerw p0.d, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1.f64.f64(double* %a, double* %b)
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ret <vscale x 2 x i1> %out
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}
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;
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; WHILEWR
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;
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define <vscale x 16 x i1> @whilewr_i8(i8* %a, i8* %b) {
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; CHECK-LABEL: whilewr_i8:
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; CHECK: whilewr p0.b, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilewr.b.nx16i1(i8* %a, i8* %b)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 8 x i1> @whilewr_i16(i16* %a, i16* %b) {
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; CHECK-LABEL: whilewr_i16:
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; CHECK: whilewr p0.h, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1(i16* %a, i16* %b)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 4 x i1> @whilewr_i32(i32* %a, i32* %b) {
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; CHECK-LABEL: whilewr_i32:
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; CHECK: whilewr p0.s, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1(i32* %a, i32* %b)
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ret <vscale x 4 x i1> %out
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}
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define <vscale x 2 x i1> @whilewr_i64(i64* %a, i64* %b) {
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; CHECK-LABEL: whilewr_i64:
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; CHECK: whilewr p0.d, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1(i64* %a, i64* %b)
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ret <vscale x 2 x i1> %out
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}
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define <vscale x 8 x i1> @whilewr_bfloat(bfloat* %a, bfloat* %b) {
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; CHECK-LABEL: whilewr_bfloat:
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; CHECK: whilewr p0.h, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 8 x i1> @whilewr_half(half* %a, half* %b) {
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; CHECK-LABEL: whilewr_half:
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; CHECK: whilewr p0.h, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.f16.f16(half* %a, half* %b)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 4 x i1> @whilewr_float(float* %a, float* %b) {
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; CHECK-LABEL: whilewr_float:
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; CHECK: whilewr p0.s, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1.f32.f32(float* %a, float* %b)
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ret <vscale x 4 x i1> %out
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}
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define <vscale x 2 x i1> @whilewr_double(double* %a, double* %b) {
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; CHECK-LABEL: whilewr_double:
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; CHECK: whilewr p0.d, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1.f64.f64(double* %a, double* %b)
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ret <vscale x 2 x i1> %out
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.whilerw.b.nx16i1(i8* %a, i8* %b)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1(i16* %a, i16* %b)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1(i32* %a, i32* %b)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1(i64* %a, i64* %b)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.f16.f16(half* %a, half* %b)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1.f32.f32(float* %a, float* %b)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1.f64.f64(double* %a, double* %b)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.whilewr.b.nx16i1(i8* %a, i8* %b)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1(i16* %a, i16* %b)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1(i32* %a, i32* %b)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1(i64* %a, i64* %b)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.f16.f16(half* %a, half* %b)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1.f32.f32(float* %a, float* %b)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1.f64.f64(double* %a, double* %b)
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