100 lines
4.2 KiB
LLVM
100 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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define <vscale x 2 x i64> @sti64ldi64(<vscale x 2 x i64>* nocapture %P, <vscale x 2 x i64> %v) {
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; CHECK-LABEL: sti64ldi64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: ret
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entry:
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%arrayidx0 = getelementptr inbounds <vscale x 2 x i64>, <vscale x 2 x i64>* %P, i64 1
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store <vscale x 2 x i64> %v, <vscale x 2 x i64>* %arrayidx0
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%arrayidx1 = getelementptr inbounds <vscale x 2 x i64>, <vscale x 2 x i64>* %P, i64 1
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%0 = load <vscale x 2 x i64>, <vscale x 2 x i64>* %arrayidx1
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x double> @stf64ldf64(<vscale x 2 x double>* nocapture %P, <vscale x 2 x double> %v) {
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; CHECK-LABEL: stf64ldf64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: ret
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entry:
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%arrayidx0 = getelementptr inbounds <vscale x 2 x double>, <vscale x 2 x double>* %P, i64 1
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store <vscale x 2 x double> %v, <vscale x 2 x double>* %arrayidx0
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%arrayidx1 = getelementptr inbounds <vscale x 2 x double>, <vscale x 2 x double>* %P, i64 1
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%0 = load <vscale x 2 x double>, <vscale x 2 x double>* %arrayidx1
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ret <vscale x 2 x double> %0
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}
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define <vscale x 2 x i64> @sti32ldi32ext(<vscale x 2 x i32>* nocapture %P, <vscale x 2 x i64> %v) {
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; CHECK-LABEL: sti32ldi32ext:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: sxtw z1.d, p0/m, z0.d
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; CHECK-NEXT: st1w { z0.d }, p0, [x0]
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; CHECK-NEXT: mov z0.d, z1.d
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; CHECK-NEXT: ret
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entry:
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%0 = trunc <vscale x 2 x i64> %v to <vscale x 2 x i32>
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store <vscale x 2 x i32> %0, <vscale x 2 x i32>* %P
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%1 = load <vscale x 2 x i32>, <vscale x 2 x i32>* %P
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%2 = sext <vscale x 2 x i32> %1 to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %2
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}
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define <2 x i64> @sti64ldfixedi64(<vscale x 2 x i64>* nocapture %P, <vscale x 2 x i64> %v) {
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; CHECK-LABEL: sti64ldfixedi64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: ldr q0, [x0, x8]
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; CHECK-NEXT: ret
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entry:
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%arrayidx0 = getelementptr inbounds <vscale x 2 x i64>, <vscale x 2 x i64>* %P, i64 1
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store <vscale x 2 x i64> %v, <vscale x 2 x i64>* %arrayidx0
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%arrayidx1 = bitcast <vscale x 2 x i64>* %arrayidx0 to <2 x i64>*
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%0 = load <2 x i64>, <2 x i64>* %arrayidx1
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ret <2 x i64> %0
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}
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define <vscale x 4 x i32> @sti64ldi32(<vscale x 2 x i64>* nocapture %P, <vscale x 2 x i64> %v) {
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; CHECK-LABEL: sti64ldi32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, #1, mul vl]
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <vscale x 2 x i64>* %P to <vscale x 4 x i32>*
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%arrayidx0 = getelementptr inbounds <vscale x 2 x i64>, <vscale x 2 x i64>* %P, i64 1
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store <vscale x 2 x i64> %v, <vscale x 2 x i64>* %arrayidx0
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%arrayidx1 = getelementptr inbounds <vscale x 4 x i32>, <vscale x 4 x i32>* %0, i64 1
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%1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %arrayidx1
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ret <vscale x 4 x i32> %1
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}
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define <vscale x 2 x i64> @stf64ldi64(<vscale x 2 x double>* nocapture %P, <vscale x 2 x double> %v) {
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; CHECK-LABEL: stf64ldi64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #1, mul vl]
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <vscale x 2 x double>* %P to <vscale x 2 x i64>*
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%arrayidx0 = getelementptr inbounds <vscale x 2 x double>, <vscale x 2 x double>* %P, i64 1
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store <vscale x 2 x double> %v, <vscale x 2 x double>* %arrayidx0
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%arrayidx1 = getelementptr inbounds <vscale x 2 x i64>, <vscale x 2 x i64>* %0, i64 1
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%1 = load <vscale x 2 x i64>, <vscale x 2 x i64>* %arrayidx1
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ret <vscale x 2 x i64> %1
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}
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