llvm-for-llvmta/test/CodeGen/AArch64/GlobalISel/select-trap.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
; Function Attrs: noreturn nounwind
declare void @llvm.trap() #0
define void @foo() {
call void @llvm.trap()
ret void
}
attributes #0 = { noreturn nounwind }
...
---
name: foo
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: foo
; CHECK: BRK 1
; CHECK: RET_ReallyLR
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
RET_ReallyLR
...