36 lines
1.0 KiB
YAML
36 lines
1.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
|
|
|
--- |
|
|
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
|
|
|
define void @sdiv_s32_gpr() { ret void }
|
|
...
|
|
|
|
---
|
|
# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
|
|
# Also check that we constrain the register class of the COPY to GPR32.
|
|
name: sdiv_s32_gpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0, $w1
|
|
|
|
; CHECK-LABEL: name: sdiv_s32_gpr
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
|
|
; CHECK: $w0 = COPY [[SDIVWr]]
|
|
%0(s32) = COPY $w0
|
|
%1(s32) = COPY $w1
|
|
%2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
|
|
$w0 = COPY %2(s32)
|
|
...
|