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llvm-for-llvmta/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
...
---
name: v2s32_fpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: gpr }
- { id: 3, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: v2s32_fpr
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1
; CHECK: $s0 = COPY [[CPYi32_]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(<2 x s32>) = COPY $d0
%2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64)
%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
$s0 = COPY %1(s32)
RET_ReallyLR implicit $s0
...
---
name: v2s32_fpr_idx0
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: v2s32_fpr_idx0
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK: $s0 = COPY [[COPY1]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(<2 x s32>) = COPY $d0
%2:gpr(s64) = G_CONSTANT i64 0
%3:fpr(s64) = COPY %2(s64)
%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
$s0 = COPY %1(s32)
RET_ReallyLR implicit $s0
...
---
name: v2s64_fpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: gpr }
- { id: 3, class: fpr }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s64_fpr
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 2
; CHECK: $d0 = COPY [[CPYi64_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s64>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 2
%3:fpr(s64) = COPY %2(s64)
%1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
$d0 = COPY %1(s64)
RET_ReallyLR implicit $d0
...
---
name: v4s16_fpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: gpr }
- { id: 3, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: v4s16_fpr
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<4 x s16>) = COPY $d0
%2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64)
%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64)
%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr_zext
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_zext
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s64) = G_ZEXT %1
%3:fpr(s64) = COPY %2(s64)
%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %4(s16)
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr_sext
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_sext
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s64) = G_SEXT %1
%3:fpr(s64) = COPY %2(s64)
%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %4(s16)
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr_trunc
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_trunc
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s32) = G_TRUNC %1
%3:gpr(s64) = G_SEXT %2
%4:fpr(s64) = COPY %3(s64)
%5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
$h0 = COPY %5(s16)
RET_ReallyLR implicit $h0
...
---
name: v2p0
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2p0
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
; CHECK: $d0 = COPY [[CPYi64_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x p0>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 1
%1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
$d0 = COPY %1(p0)
RET_ReallyLR implicit $d0
...
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