104 lines
2.8 KiB
YAML
104 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s
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name: v2s32_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $d0
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%0:_(<2 x s32>) = COPY $d0
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%2:_(s64) = G_CONSTANT i64 1
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%1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v4s32_gpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: v4s32_gpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
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; CHECK: [[EVEC:%[0-9]+]]:fpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)
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; CHECK: $s0 = COPY [[EVEC]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%0:_(<4 x s32>) = COPY $q0
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%2:_(s64) = G_CONSTANT i64 0
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%1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %2(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s64_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 2
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; CHECK: [[EVEC:%[0-9]+]]:fpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
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; CHECK: $d0 = COPY [[EVEC]](s64)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s64>) = COPY $q0
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%2:_(s64) = G_CONSTANT i64 2
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%1:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %2(s64)
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: v4s16_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $d0
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; CHECK-LABEL: name: v4s16_fpr
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
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; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1
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; CHECK: [[EVEC:%[0-9]+]]:fpr(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s16>), [[C]](s64)
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; CHECK: $h0 = COPY [[EVEC]](s16)
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; CHECK: RET_ReallyLR implicit $h0
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%0:_(<4 x s16>) = COPY $d0
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%2:_(s64) = G_CONSTANT i64 1
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%1:_(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %2(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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