285 lines
9.7 KiB
YAML
285 lines
9.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombinerhelper-only-enable-rule="not_cmp_fold" %s -o - -verify-machineinstrs | FileCheck %s
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# Need asserts for the only-enable-rule to work.
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# REQUIRES: asserts
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# Check that we fold an compare result inverted into just inverting the condition code.
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---
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name: icmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: fcmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: fcmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](s64), [[C]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_FCMP floatpred(ogt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_not_xor_with_1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_not_xor_with_1
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 0
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_not_xor_with_wrong_bool_contents
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; Even though bit 0 of the constant is 1, we require zero in the upper bits
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; for our aarch64's zero-or-one boolean contents.
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; CHECK-LABEL: name: icmp_not_xor_with_wrong_bool_contents
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
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; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C1]]
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; CHECK: $w0 = COPY [[XOR]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s32) = G_CONSTANT i32 7
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%3:_(s32) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s32) = G_XOR %3, %2
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_multiple_use
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_multiple_use
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C1]]
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; CHECK: %other_use:_(s1) = G_AND [[ICMP]], [[C1]]
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; CHECK: %other_use_ext:_(s32) = G_ANYEXT %other_use(s1)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: $w1 = COPY %other_use_ext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%other_use:_(s1) = G_AND %3, %2
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%other_use_ext:_(s32) = G_ANYEXT %other_use(s1)
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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$w1 = COPY %other_use_ext
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_vector
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: icmp_vector
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: %splat_op2:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s1>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), %splat_op2
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; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[ICMP]](<4 x s1>)
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; CHECK: $q0 = COPY [[ANYEXT]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 5
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%splat_op2:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %1, %1
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%2:_(s1) = G_CONSTANT i1 1
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%splat_true:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
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%3:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %splat_op2
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%4:_(<4 x s1>) = G_XOR %3, %splat_true
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%5:_(<4 x s32>) = G_ANYEXT %4
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$q0 = COPY %5(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: icmp_and_icmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_and_icmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[COPY]](s64), [[C]]
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; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
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%5:_(s1) = G_AND %3, %4
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%6:_(s1) = G_XOR %5, %2
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%7:_(s32) = G_ANYEXT %6
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$w0 = COPY %7(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_or_icmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_or_icmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[COPY]](s64), [[C]]
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; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP]], [[ICMP1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
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%5:_(s1) = G_OR %3, %4
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%6:_(s1) = G_XOR %5, %2
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%7:_(s32) = G_ANYEXT %6
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$w0 = COPY %7(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_and_icmp_or_icmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_and_icmp_or_icmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[COPY]](s64), [[C]]
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; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]
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; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[C]]
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; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[OR]], [[ICMP2]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
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%5:_(s1) = G_AND %3, %4
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%6:_(s1) = G_ICMP intpred(ne), %0(s64), %1
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%7:_(s1) = G_OR %5, %6
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%8:_(s1) = G_XOR %7, %2
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%9:_(s32) = G_ANYEXT %8
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$w0 = COPY %9(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_and_trunc
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_and_trunc
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
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; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP]], [[TRUNC]]
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; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[AND]], [[C1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_TRUNC %0(s64)
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%5:_(s1) = G_AND %3, %4
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%6:_(s1) = G_XOR %5, %2
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%7:_(s32) = G_ANYEXT %6
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$w0 = COPY %7(s32)
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RET_ReallyLR implicit $w0
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...
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