226 lines
8.7 KiB
LLVM
226 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -disable-expand-reductions -stop-after=irtranslator %s -o - | FileCheck %s
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declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
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declare double @llvm.vector.reduce.fmul.v4f64(double, <4 x double>)
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define float @fadd_seq(float %start, <4 x float> %vec) {
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; CHECK-LABEL: name: fadd_seq
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q1, $s0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_SEQ_FADD [[COPY]](s32), [[COPY1]](<4 x s32>)
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; CHECK: $s0 = COPY [[VECREDUCE_SEQ_FADD]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)
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ret float %res
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}
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define float @fadd_fast(float %start, <4 x float> %vec) {
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; CHECK-LABEL: name: fadd_fast
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q1, $s0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = reassoc G_VECREDUCE_FADD [[COPY1]](<4 x s32>)
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; CHECK: [[FADD:%[0-9]+]]:_(s32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
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; CHECK: $s0 = COPY [[FADD]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%res = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)
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ret float %res
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}
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define double @fmul_seq(double %start, <4 x double> %vec) {
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; CHECK-LABEL: name: fmul_seq
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $d0, $q1, $q2
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)
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; CHECK: [[VECREDUCE_SEQ_FMUL:%[0-9]+]]:_(s64) = G_VECREDUCE_SEQ_FMUL [[COPY]](s64), [[CONCAT_VECTORS]](<4 x s64>)
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; CHECK: $d0 = COPY [[VECREDUCE_SEQ_FMUL]](s64)
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; CHECK: RET_ReallyLR implicit $d0
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%res = call double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)
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ret double %res
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}
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define double @fmul_fast(double %start, <4 x double> %vec) {
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; CHECK-LABEL: name: fmul_fast
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $d0, $q1, $q2
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)
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; CHECK: [[VECREDUCE_FMUL:%[0-9]+]]:_(s64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x s64>)
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; CHECK: [[FMUL:%[0-9]+]]:_(s64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]
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; CHECK: $d0 = COPY [[FMUL]](s64)
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; CHECK: RET_ReallyLR implicit $d0
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%res = call reassoc double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)
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ret double %res
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}
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declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
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declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
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define float @fmax(<4 x float> %vec) {
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; CHECK-LABEL: name: fmax
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[COPY]](<4 x s32>)
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; CHECK: $s0 = COPY [[VECREDUCE_FMAX]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %vec)
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ret float %res
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}
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define float @fmin(<4 x float> %vec) {
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; CHECK-LABEL: name: fmin
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[COPY]](<4 x s32>)
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; CHECK: $s0 = COPY [[VECREDUCE_FMIN]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)
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ret float %res
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}
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define float @fmin_nnan(<4 x float> %vec) {
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; CHECK-LABEL: name: fmin_nnan
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMIN [[COPY]](<4 x s32>)
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; CHECK: $s0 = COPY [[VECREDUCE_FMIN]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%res = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)
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ret float %res
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}
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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define i32 @add(<4 x i32> %vec) {
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; CHECK-LABEL: name: add
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>)
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define i32 @mul(<4 x i32> %vec) {
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; CHECK-LABEL: name: mul
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_MUL:%[0-9]+]]:_(s32) = G_VECREDUCE_MUL [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_MUL]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
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define i32 @and(<4 x i32> %vec) {
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; CHECK-LABEL: name: and
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_AND:%[0-9]+]]:_(s32) = G_VECREDUCE_AND [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_AND]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
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define i32 @or(<4 x i32> %vec) {
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; CHECK-LABEL: name: or
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_OR:%[0-9]+]]:_(s32) = G_VECREDUCE_OR [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_OR]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
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define i32 @xor(<4 x i32> %vec) {
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; CHECK-LABEL: name: xor
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_XOR:%[0-9]+]]:_(s32) = G_VECREDUCE_XOR [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_XOR]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
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declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
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declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
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declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
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define i32 @smax(<4 x i32> %vec) {
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; CHECK-LABEL: name: smax
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_SMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_SMAX [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_SMAX]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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define i32 @smin(<4 x i32> %vec) {
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; CHECK-LABEL: name: smin
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_SMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_SMIN [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_SMIN]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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define i32 @umax(<4 x i32> %vec) {
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; CHECK-LABEL: name: umax
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_UMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_UMAX [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_UMAX]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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define i32 @umin(<4 x i32> %vec) {
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; CHECK-LABEL: name: umin
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[VECREDUCE_UMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_UMIN [[COPY]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_UMIN]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)
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ret i32 %res
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}
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