48 lines
1.2 KiB
LLVM
48 lines
1.2 KiB
LLVM
; RUN: opt %s -analyze -divergence -use-gpu-divergence-analysis | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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define i32 @daorder(i32 %n) {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'daorder'
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entry:
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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%cond = icmp slt i32 %tid, 0
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br i1 %cond, label %A, label %B ; divergent
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; CHECK: DIVERGENT: br i1 %cond,
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A:
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%defAtA = add i32 %n, 1 ; uniform
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; CHECK-NOT: DIVERGENT: %defAtA =
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br label %C
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B:
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%defAtB = add i32 %n, 2 ; uniform
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; CHECK-NOT: DIVERGENT: %defAtB =
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br label %C
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C:
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%defAtC = phi i32 [ %defAtA, %A ], [ %defAtB, %B ] ; divergent
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; CHECK: DIVERGENT: %defAtC =
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br label %D
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D:
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%i = phi i32 [0, %C], [ %i.inc, %E ] ; uniform
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; CHECK-NOT: DIVERGENT: %i = phi
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br label %E
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E:
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%i.inc = add i32 %i, 1
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%loopCnt = icmp slt i32 %i.inc, %n
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; CHECK-NOT: DIVERGENT: %loopCnt =
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br i1 %loopCnt, label %D, label %exit
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exit:
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ret i32 %n
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}
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
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!nvvm.annotations = !{!0}
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!0 = !{i32 (i32)* @daorder, !"kernel", i32 1}
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