109 lines
4.0 KiB
TableGen
109 lines
4.0 KiB
TableGen
//===-- CSKYInstrInfo.td - Target Description for CSKY -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the CSKY instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "CSKYInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// CSKY specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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// TODO: Add CSKY specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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class oimm<int num> : Operand<i32>,
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ImmLeaf<i32, "return isUInt<"#num#">(Imm - 1);"> {
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let EncoderMethod = "getOImmOpValue";
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}
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class uimm<int num, int shift = 0> : Operand<i32>,
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ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
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let EncoderMethod = "getImmOpValue<"#shift#">";
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}
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class simm<int num, int shift = 0> : Operand<i32>,
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ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
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let EncoderMethod = "getImmOpValue<"#shift#">";
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}
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def nimm_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~N->getSExtValue(), SDLoc(N), MVT::i32);
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}]>;
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class nimm<int num> : Operand<i32>,
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ImmLeaf<i32, "return isUInt<"#num#">(~Imm);", nimm_XFORM> {
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}
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def oimm12 : oimm<12>;
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def nimm12 : nimm<12>;
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def uimm5 : uimm<5>;
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def uimm12 : uimm<12>;
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//===----------------------------------------------------------------------===//
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// Instruction definitions.
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//===----------------------------------------------------------------------===//
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class TriOpFrag<dag res> : PatFrag<(ops node: $LHS, node:$MHS, node:$RHS), res>;
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class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
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class UnOpFrag<dag res> : PatFrag<(ops node:$Src), res>;
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def ADDI32 : I_12<0x0, "addi32", add, oimm12>;
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def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;
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def ANDI32 : I_12<0x2, "andi32", and, uimm12>;
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def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;
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def XORI32 : I_12<0x4, "xori32", xor, uimm12>;
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def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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[(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
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def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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[(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
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def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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[(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
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def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,
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BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;
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def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,
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BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;
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def AND32 : R_YXZ_SP_F1<0x8, 0x1,
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BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;
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def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,
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BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;
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def OR32: R_YXZ_SP_F1<0x9, 0x1,
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BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;
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def XOR32 : R_YXZ_SP_F1<0x9, 0x2,
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BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;
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def NOR32 : R_YXZ_SP_F1<0x9, 0x4,
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BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;
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def LSL32 : R_YXZ_SP_F1<0x10, 0x1,
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BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;
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def LSR32 : R_YXZ_SP_F1<0x10, 0x2,
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BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;
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def ASR32 : R_YXZ_SP_F1<0x10, 0x4,
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BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;
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def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
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BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
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def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
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BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
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def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
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BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
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def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
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"not", [(set GPR:$rz, (not GPR:$rx))]>;
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