146 lines
5.3 KiB
C++
146 lines
5.3 KiB
C++
//===-- BPFISelLowering.h - BPF DAG Lowering Interface ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that BPF uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
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#define LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
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#include "BPF.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class BPFSubtarget;
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namespace BPFISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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RET_FLAG,
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CALL,
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SELECT_CC,
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BR_CC,
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Wrapper,
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MEMCPY
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};
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}
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class BPFTargetLowering : public TargetLowering {
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public:
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explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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// This method returns the name of a target specific DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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// This method decides whether folding a constant offset
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// with the given GlobalAddress is legal.
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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bool getHasAlu32() const { return HasAlu32; }
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bool getHasJmp32() const { return HasJmp32; }
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bool getHasJmpExt() const { return HasJmpExt; }
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
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private:
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// Control Instruction Selection Features
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bool HasAlu32;
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bool HasJmp32;
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bool HasJmpExt;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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// Lower the result values of a call, copying them out of physregs into vregs
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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// Maximum number of arguments to a call
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static const unsigned MaxArgs;
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// Lower a call into CALLSEQ_START - BPFISD:CALL - CALLSEQ_END chain
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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// Lower incoming arguments, copy physregs into vregs
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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EVT getOptimalMemOpType(const MemOp &Op,
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const AttributeList &FuncAttributes) const override {
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return Op.size() >= 8 ? MVT::i64 : MVT::i32;
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}
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override {
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return true;
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}
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// Prevent reducing load width during SelectionDag phase.
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// Otherwise, we may transform the following
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// ctx = ctx + reloc_offset
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// ... (*(u32 *)ctx) & 0x8000...
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// to
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// ctx = ctx + reloc_offset
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// ... (*(u8 *)(ctx + 1)) & 0x80 ...
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// which will be rejected by the verifier.
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bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
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EVT NewVT) const override {
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return false;
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}
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// isTruncateFree - Return true if it's free to truncate a value of
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// type Ty1 to type Ty2. e.g. On BPF at alu32 mode, it's free to truncate
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// a i64 value in register R1 to i32 by referencing its sub-register W1.
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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// For 32bit ALU result zext to 64bit is free.
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bool isZExtFree(Type *Ty1, Type *Ty2) const override;
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bool isZExtFree(EVT VT1, EVT VT2) const override;
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unsigned EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, unsigned Reg,
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bool isSigned) const;
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MachineBasicBlock * EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
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MachineBasicBlock *BB)
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const;
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};
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}
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#endif
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