269 lines
9.4 KiB
C++
269 lines
9.4 KiB
C++
//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ARMHazardRecognizer.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<int> DataBankMask("arm-data-bank-mask", cl::init(-1),
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cl::Hidden);
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static cl::opt<bool> AssumeITCMConflict("arm-assume-itcm-bankconflict",
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cl::init(false), cl::Hidden);
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static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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const TargetRegisterInfo &TRI) {
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// FIXME: Detect integer instructions properly.
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const MCInstrDesc &MCID = MI->getDesc();
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unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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if (MI->mayStore())
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return false;
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unsigned Opcode = MCID.getOpcode();
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if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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return false;
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}
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ScheduleHazardRecognizer::HazardType
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ARMHazardRecognizerFPMLx::getHazardType(SUnit *SU, int Stalls) {
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assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugInstr()) {
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// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
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// a VMLA / VMLS will cause 4 cycle stall.
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const MCInstrDesc &MCID = MI->getDesc();
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if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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MachineInstr *DefMI = LastMI;
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const MCInstrDesc &LastMCID = LastMI->getDesc();
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const MachineFunction *MF = MI->getParent()->getParent();
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const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
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MF->getSubtarget().getInstrInfo());
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// Skip over one non-VFP / NEON instruction.
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if (!LastMI->isBarrier() &&
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!(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) &&
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(LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
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MachineBasicBlock::iterator I = LastMI;
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if (I != LastMI->getParent()->begin()) {
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I = std::prev(I);
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DefMI = &*I;
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}
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}
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if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
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(TII.canCauseFpMLxStall(MI->getOpcode()) ||
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hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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// Try to schedule another instruction for the next 4 cycles.
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if (FpMLxStalls == 0)
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FpMLxStalls = 4;
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return Hazard;
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}
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}
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}
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return NoHazard;
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}
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void ARMHazardRecognizerFPMLx::Reset() {
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LastMI = nullptr;
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FpMLxStalls = 0;
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}
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void ARMHazardRecognizerFPMLx::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugInstr()) {
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LastMI = MI;
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FpMLxStalls = 0;
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}
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}
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void ARMHazardRecognizerFPMLx::AdvanceCycle() {
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if (FpMLxStalls && --FpMLxStalls == 0)
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// Stalled for 4 cycles but still can't schedule any other instructions.
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LastMI = nullptr;
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}
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void ARMHazardRecognizerFPMLx::RecedeCycle() {
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llvm_unreachable("reverse ARM hazard checking unsupported");
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}
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///////// Bank conflicts handled as hazards //////////////
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static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp,
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int64_t &Offset) {
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uint64_t TSFlags = MI.getDesc().TSFlags;
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unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
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unsigned IndexMode =
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(TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
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// Address mode tells us what we want to know about operands for T2
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// instructions (but not size). It tells us size (but not about operands)
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// for T1 instructions.
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switch (AddrMode) {
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default:
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return false;
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case ARMII::AddrModeT2_i8:
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// t2LDRBT, t2LDRB_POST, t2LDRB_PRE, t2LDRBi8,
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// t2LDRHT, t2LDRH_POST, t2LDRH_PRE, t2LDRHi8,
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// t2LDRSBT, t2LDRSB_POST, t2LDRSB_PRE, t2LDRSBi8,
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// t2LDRSHT, t2LDRSH_POST, t2LDRSH_PRE, t2LDRSHi8,
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// t2LDRT, t2LDR_POST, t2LDR_PRE, t2LDRi8
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BaseOp = &MI.getOperand(1);
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Offset = (IndexMode == ARMII::IndexModePost)
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? 0
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: (IndexMode == ARMII::IndexModePre ||
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IndexMode == ARMII::IndexModeUpd)
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? MI.getOperand(3).getImm()
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: MI.getOperand(2).getImm();
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return true;
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case ARMII::AddrModeT2_i12:
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// t2LDRBi12, t2LDRHi12
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// t2LDRSBi12, t2LDRSHi12
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// t2LDRi12
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BaseOp = &MI.getOperand(1);
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Offset = MI.getOperand(2).getImm();
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return true;
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case ARMII::AddrModeT2_i8s4:
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// t2LDRD_POST, t2LDRD_PRE, t2LDRDi8
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BaseOp = &MI.getOperand(2);
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Offset = (IndexMode == ARMII::IndexModePost)
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? 0
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: (IndexMode == ARMII::IndexModePre ||
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IndexMode == ARMII::IndexModeUpd)
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? MI.getOperand(4).getImm()
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: MI.getOperand(3).getImm();
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return true;
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case ARMII::AddrModeT1_1:
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// tLDRBi, tLDRBr (watch out!), TLDRSB
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case ARMII::AddrModeT1_2:
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// tLDRHi, tLDRHr (watch out!), TLDRSH
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case ARMII::AddrModeT1_4:
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// tLDRi, tLDRr (watch out!)
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BaseOp = &MI.getOperand(1);
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Offset = MI.getOperand(2).isImm() ? MI.getOperand(2).getImm() : 0;
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return MI.getOperand(2).isImm();
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}
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return false;
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}
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ARMBankConflictHazardRecognizer::ARMBankConflictHazardRecognizer(
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const ScheduleDAG *DAG, int64_t CPUBankMask, bool CPUAssumeITCMConflict)
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: ScheduleHazardRecognizer(), MF(DAG->MF), DL(DAG->MF.getDataLayout()),
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DataMask(DataBankMask.getNumOccurrences() ? int64_t(DataBankMask)
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: CPUBankMask),
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AssumeITCMBankConflict(AssumeITCMConflict.getNumOccurrences()
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? AssumeITCMConflict
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: CPUAssumeITCMConflict) {
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MaxLookAhead = 1;
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}
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ScheduleHazardRecognizer::HazardType
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ARMBankConflictHazardRecognizer::CheckOffsets(unsigned O0, unsigned O1) {
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return (((O0 ^ O1) & DataMask) != 0) ? NoHazard : Hazard;
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}
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ScheduleHazardRecognizer::HazardType
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ARMBankConflictHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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MachineInstr &L0 = *SU->getInstr();
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if (!L0.mayLoad() || L0.mayStore() || L0.getNumMemOperands() != 1)
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return NoHazard;
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auto MO0 = *L0.memoperands().begin();
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auto BaseVal0 = MO0->getValue();
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auto BasePseudoVal0 = MO0->getPseudoValue();
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int64_t Offset0 = 0;
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if (MO0->getSize() > 4)
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return NoHazard;
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bool SPvalid = false;
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const MachineOperand *SP = nullptr;
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int64_t SPOffset0 = 0;
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for (auto L1 : Accesses) {
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auto MO1 = *L1->memoperands().begin();
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auto BaseVal1 = MO1->getValue();
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auto BasePseudoVal1 = MO1->getPseudoValue();
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int64_t Offset1 = 0;
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// Pointers to the same object
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if (BaseVal0 && BaseVal1) {
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const Value *Ptr0, *Ptr1;
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Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true);
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Ptr1 = GetPointerBaseWithConstantOffset(BaseVal1, Offset1, DL, true);
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if (Ptr0 == Ptr1 && Ptr0)
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return CheckOffsets(Offset0, Offset1);
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}
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if (BasePseudoVal0 && BasePseudoVal1 &&
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BasePseudoVal0->kind() == BasePseudoVal1->kind() &&
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BasePseudoVal0->kind() == PseudoSourceValue::FixedStack) {
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// Spills/fills
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auto FS0 = cast<FixedStackPseudoSourceValue>(BasePseudoVal0);
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auto FS1 = cast<FixedStackPseudoSourceValue>(BasePseudoVal1);
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Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex());
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Offset1 = MF.getFrameInfo().getObjectOffset(FS1->getFrameIndex());
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return CheckOffsets(Offset0, Offset1);
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}
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// Constant pools (likely in ITCM)
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if (BasePseudoVal0 && BasePseudoVal1 &&
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BasePseudoVal0->kind() == BasePseudoVal1->kind() &&
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BasePseudoVal0->isConstantPool() && AssumeITCMBankConflict)
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return Hazard;
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// Is this a stack pointer-relative access? We could in general try to
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// use "is this the same register and is it unchanged?", but the
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// memory operand tracking is highly likely to have already found that.
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// What we're after here is bank conflicts between different objects in
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// the stack frame.
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if (!SPvalid) { // set up SP
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if (!getBaseOffset(L0, SP, SPOffset0) || SP->getReg().id() != ARM::SP)
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SP = nullptr;
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SPvalid = true;
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}
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if (SP) {
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int64_t SPOffset1;
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const MachineOperand *SP1;
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if (getBaseOffset(*L1, SP1, SPOffset1) && SP1->getReg().id() == ARM::SP)
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return CheckOffsets(SPOffset0, SPOffset1);
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}
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}
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return NoHazard;
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}
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void ARMBankConflictHazardRecognizer::Reset() { Accesses.clear(); }
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void ARMBankConflictHazardRecognizer::EmitInstruction(SUnit *SU) {
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MachineInstr &MI = *SU->getInstr();
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if (!MI.mayLoad() || MI.mayStore() || MI.getNumMemOperands() != 1)
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return;
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auto MO = *MI.memoperands().begin();
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uint64_t Size1 = MO->getSize();
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if (Size1 > 4)
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return;
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Accesses.push_back(&MI);
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}
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void ARMBankConflictHazardRecognizer::AdvanceCycle() { Accesses.clear(); }
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void ARMBankConflictHazardRecognizer::RecedeCycle() { Accesses.clear(); }
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