961 lines
31 KiB
C++
961 lines
31 KiB
C++
//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#include "SIDefines.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Support/Alignment.h"
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struct amd_kernel_code_t;
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namespace llvm {
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struct Align;
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class Argument;
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class Function;
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class GCNSubtarget;
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class GlobalValue;
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class MCRegisterClass;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class StringRef;
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class Triple;
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namespace amdhsa {
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struct kernel_descriptor_t;
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}
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namespace AMDGPU {
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struct IsaVersion;
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/// \returns HSA OS ABI Version identification.
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Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 2,
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/// false otherwise.
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bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 3,
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/// false otherwise.
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bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
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struct GcnBufferFormatInfo {
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unsigned Format;
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unsigned BitsPerComp;
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unsigned NumComponents;
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unsigned NumFormat;
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unsigned DataFormat;
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};
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#define GET_MIMGBaseOpcode_DECL
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#define GET_MIMGDim_DECL
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#define GET_MIMGEncoding_DECL
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#define GET_MIMGLZMapping_DECL
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#define GET_MIMGMIPMapping_DECL
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#include "AMDGPUGenSearchableTables.inc"
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namespace IsaInfo {
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enum {
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// The closed Vulkan driver sets 96, which limits the wave count to 8 but
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// doesn't spill SGPRs as much as when 80 is set.
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FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
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TRAP_NUM_SGPRS = 16
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};
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enum class TargetIDSetting {
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Unsupported,
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Any,
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Off,
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On
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};
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class AMDGPUTargetID {
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private:
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TargetIDSetting XnackSetting;
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TargetIDSetting SramEccSetting;
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public:
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explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
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~AMDGPUTargetID() = default;
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/// \return True if the current xnack setting is not "Unsupported".
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bool isXnackSupported() const {
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return XnackSetting != TargetIDSetting::Unsupported;
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}
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/// \returns True if the current xnack setting is "On" or "Any".
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bool isXnackOnOrAny() const {
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return XnackSetting == TargetIDSetting::On ||
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XnackSetting == TargetIDSetting::Any;
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}
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/// \returns True if current xnack setting is "On" or "Off",
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/// false otherwise.
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bool isXnackOnOrOff() const {
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return getXnackSetting() == TargetIDSetting::On ||
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getXnackSetting() == TargetIDSetting::Off;
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}
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/// \returns The current xnack TargetIDSetting, possible options are
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/// "Unsupported", "Any", "Off", and "On".
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TargetIDSetting getXnackSetting() const {
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return XnackSetting;
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}
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/// Sets xnack setting to \p NewXnackSetting.
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void setXnackSetting(TargetIDSetting NewXnackSetting) {
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XnackSetting = NewXnackSetting;
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}
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/// \return True if the current sramecc setting is not "Unsupported".
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bool isSramEccSupported() const {
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return SramEccSetting != TargetIDSetting::Unsupported;
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}
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/// \returns True if the current sramecc setting is "On" or "Any".
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bool isSramEccOnOrAny() const {
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return SramEccSetting == TargetIDSetting::On ||
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SramEccSetting == TargetIDSetting::Any;
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}
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/// \returns True if current sramecc setting is "On" or "Off",
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/// false otherwise.
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bool isSramEccOnOrOff() const {
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return getSramEccSetting() == TargetIDSetting::On ||
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getSramEccSetting() == TargetIDSetting::Off;
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}
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/// \returns The current sramecc TargetIDSetting, possible options are
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/// "Unsupported", "Any", "Off", and "On".
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TargetIDSetting getSramEccSetting() const {
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return SramEccSetting;
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}
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/// Sets sramecc setting to \p NewSramEccSetting.
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void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
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SramEccSetting = NewSramEccSetting;
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}
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void setTargetIDFromFeaturesString(StringRef FS);
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void setTargetIDFromTargetIDStream(StringRef TargetID);
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};
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/// Streams isa version string for given subtarget \p STI into \p Stream.
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void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
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/// \returns Wavefront size for given subtarget \p STI.
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unsigned getWavefrontSize(const MCSubtargetInfo *STI);
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/// \returns Local memory size in bytes for given subtarget \p STI.
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unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
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/// \returns Number of execution units per compute unit for given subtarget \p
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/// STI.
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unsigned getEUsPerCU(const MCSubtargetInfo *STI);
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/// \returns Maximum number of work groups per compute unit for given subtarget
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/// \p STI and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum number of waves per execution unit for given subtarget \p
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/// STI.
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unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
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/// \returns Maximum number of waves per execution unit for given subtarget \p
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/// STI without any kind of limitation.
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unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
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/// \returns Number of waves per execution unit required to support the given \p
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/// FlatWorkGroupSize.
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unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum flat work group size for given subtarget \p STI.
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unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
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/// \returns Maximum flat work group size for given subtarget \p STI.
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unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
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/// \returns Number of waves per work group for given subtarget \p STI and
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/// \p FlatWorkGroupSize.
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unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize);
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/// \returns SGPR allocation granularity for given subtarget \p STI.
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unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
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/// \returns SGPR encoding granularity for given subtarget \p STI.
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unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
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/// \returns Total number of SGPRs for given subtarget \p STI.
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unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
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/// \returns Addressable number of SGPRs for given subtarget \p STI.
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unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
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/// \returns Minimum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
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/// \returns Maximum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
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bool Addressable);
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/// \returns Number of extra SGPRs implicitly required by given subtarget \p
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/// STI when the given special registers are used.
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
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bool FlatScrUsed, bool XNACKUsed);
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/// \returns Number of extra SGPRs implicitly required by given subtarget \p
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/// STI when the given special registers are used. XNACK is inferred from
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/// \p STI.
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
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bool FlatScrUsed);
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/// \returns Number of SGPR blocks needed for given subtarget \p STI when
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/// \p NumSGPRs are used. \p NumSGPRs should already include any special
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/// register counts.
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unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
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/// \returns VGPR allocation granularity for given subtarget \p STI.
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///
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/// For subtargets which support it, \p EnableWavefrontSize32 should match
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/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
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unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
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Optional<bool> EnableWavefrontSize32 = None);
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/// \returns VGPR encoding granularity for given subtarget \p STI.
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///
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/// For subtargets which support it, \p EnableWavefrontSize32 should match
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/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
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unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
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Optional<bool> EnableWavefrontSize32 = None);
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/// \returns Total number of VGPRs for given subtarget \p STI.
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unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
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/// \returns Addressable number of VGPRs for given subtarget \p STI.
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unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
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/// \returns Minimum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
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/// \returns Maximum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
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/// \returns Number of VGPR blocks needed for given subtarget \p STI when
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/// \p NumVGPRs are used.
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///
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/// For subtargets which support it, \p EnableWavefrontSize32 should match the
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/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
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unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
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Optional<bool> EnableWavefrontSize32 = None);
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} // end namespace IsaInfo
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LLVM_READONLY
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
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LLVM_READONLY
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int getSOPPWithRelaxation(uint16_t Opcode);
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struct MIMGBaseOpcodeInfo {
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MIMGBaseOpcode BaseOpcode;
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bool Store;
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bool Atomic;
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bool AtomicX2;
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bool Sampler;
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bool Gather4;
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uint8_t NumExtraArgs;
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bool Gradients;
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bool G16;
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bool Coordinates;
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bool LodOrClampOrMip;
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bool HasD16;
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};
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LLVM_READONLY
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const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
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struct MIMGDimInfo {
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MIMGDim Dim;
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uint8_t NumCoords;
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uint8_t NumGradients;
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bool DA;
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uint8_t Encoding;
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const char *AsmSuffix;
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};
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LLVM_READONLY
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const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
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LLVM_READONLY
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const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
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LLVM_READONLY
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const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
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struct MIMGLZMappingInfo {
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MIMGBaseOpcode L;
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MIMGBaseOpcode LZ;
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};
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struct MIMGMIPMappingInfo {
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MIMGBaseOpcode MIP;
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MIMGBaseOpcode NONMIP;
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};
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struct MIMGG16MappingInfo {
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MIMGBaseOpcode G;
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MIMGBaseOpcode G16;
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};
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LLVM_READONLY
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const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
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LLVM_READONLY
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const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
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LLVM_READONLY
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const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
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LLVM_READONLY
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int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
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unsigned VDataDwords, unsigned VAddrDwords);
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LLVM_READONLY
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int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
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struct MIMGInfo {
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uint16_t Opcode;
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uint16_t BaseOpcode;
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uint8_t MIMGEncoding;
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uint8_t VDataDwords;
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uint8_t VAddrDwords;
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};
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LLVM_READONLY
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const MIMGInfo *getMIMGInfo(unsigned Opc);
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LLVM_READONLY
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int getMTBUFBaseOpcode(unsigned Opc);
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LLVM_READONLY
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int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
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LLVM_READONLY
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int getMTBUFElements(unsigned Opc);
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LLVM_READONLY
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bool getMTBUFHasVAddr(unsigned Opc);
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LLVM_READONLY
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bool getMTBUFHasSrsrc(unsigned Opc);
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LLVM_READONLY
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bool getMTBUFHasSoffset(unsigned Opc);
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LLVM_READONLY
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int getMUBUFBaseOpcode(unsigned Opc);
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LLVM_READONLY
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int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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LLVM_READONLY
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int getMUBUFElements(unsigned Opc);
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LLVM_READONLY
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bool getMUBUFHasVAddr(unsigned Opc);
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LLVM_READONLY
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bool getMUBUFHasSrsrc(unsigned Opc);
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LLVM_READONLY
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bool getMUBUFHasSoffset(unsigned Opc);
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LLVM_READONLY
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bool getSMEMIsBuffer(unsigned Opc);
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LLVM_READONLY
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const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
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uint8_t NumComponents,
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uint8_t NumFormat,
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const MCSubtargetInfo &STI);
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LLVM_READONLY
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const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
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const MCSubtargetInfo &STI);
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LLVM_READONLY
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int getMCOpcode(uint16_t Opcode, unsigned Gen);
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const MCSubtargetInfo *STI);
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amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
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const MCSubtargetInfo *STI);
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bool isGroupSegment(const GlobalValue *GV);
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bool isGlobalSegment(const GlobalValue *GV);
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bool isReadOnlySegment(const GlobalValue *GV);
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/// \returns True if constants should be emitted to .text section for given
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/// target triple \p TT, false otherwise.
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bool shouldEmitConstantsToTextSection(const Triple &TT);
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/// \returns Integer value requested using \p F's \p Name attribute.
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if requested value cannot be converted
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/// to integer.
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int getIntegerAttribute(const Function &F, StringRef Name, int Default);
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/// \returns A pair of integer values requested using \p F's \p Name attribute
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/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
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/// is false).
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if one of the requested values cannot be
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/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
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/// not present.
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired = false);
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/// Represents the counter values to wait for in an s_waitcnt instruction.
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///
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/// Large values (including the maximum possible integer) can be used to
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/// represent "don't care" waits.
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struct Waitcnt {
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unsigned VmCnt = ~0u;
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unsigned ExpCnt = ~0u;
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unsigned LgkmCnt = ~0u;
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unsigned VsCnt = ~0u;
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Waitcnt() {}
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Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
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: VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
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static Waitcnt allZero(bool HasVscnt) {
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return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
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}
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static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
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bool hasWait() const {
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return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
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}
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bool dominates(const Waitcnt &Other) const {
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return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
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LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
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}
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Waitcnt combined(const Waitcnt &Other) const {
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return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
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std::min(LgkmCnt, Other.LgkmCnt),
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std::min(VsCnt, Other.VsCnt));
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}
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};
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/// \returns Vmcnt bit mask for given isa \p Version.
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unsigned getVmcntBitMask(const IsaVersion &Version);
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/// \returns Expcnt bit mask for given isa \p Version.
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unsigned getExpcntBitMask(const IsaVersion &Version);
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/// \returns Lgkmcnt bit mask for given isa \p Version.
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unsigned getLgkmcntBitMask(const IsaVersion &Version);
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/// \returns Waitcnt bit mask for given isa \p Version.
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unsigned getWaitcntBitMask(const IsaVersion &Version);
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/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
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/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
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/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
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/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
|
|
/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
|
|
/// \p Lgkmcnt respectively.
|
|
///
|
|
/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
|
|
/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
|
|
/// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
|
|
/// \p Expcnt = \p Waitcnt[6:4]
|
|
/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10 only)
|
|
/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10+ only)
|
|
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
|
|
|
|
Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
|
|
|
|
/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
|
|
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Vmcnt);
|
|
|
|
/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
|
|
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Expcnt);
|
|
|
|
/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
|
|
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Lgkmcnt);
|
|
|
|
/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
|
|
/// \p Version.
|
|
///
|
|
/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
|
|
/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
|
|
/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
|
|
/// Waitcnt[6:4] = \p Expcnt
|
|
/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10 only)
|
|
/// Waitcnt[13:8] = \p Lgkmcnt (gfx10+ only)
|
|
/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
|
|
///
|
|
/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
|
|
/// isa \p Version.
|
|
unsigned encodeWaitcnt(const IsaVersion &Version,
|
|
unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
|
|
|
|
unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
|
|
|
|
namespace Hwreg {
|
|
|
|
LLVM_READONLY
|
|
int64_t getHwregId(const StringRef Name);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwreg(int64_t Id);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwregOffset(int64_t Offset);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwregWidth(int64_t Width);
|
|
|
|
LLVM_READNONE
|
|
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
|
|
|
|
LLVM_READNONE
|
|
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
|
|
|
|
} // namespace Hwreg
|
|
|
|
namespace Exp {
|
|
|
|
bool getTgtName(unsigned Id, StringRef &Name, int &Index);
|
|
|
|
LLVM_READONLY
|
|
unsigned getTgtId(const StringRef Name);
|
|
|
|
LLVM_READNONE
|
|
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
} // namespace Exp
|
|
|
|
namespace MTBUFFormat {
|
|
|
|
LLVM_READNONE
|
|
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
|
|
|
|
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
|
|
|
|
int64_t getDfmt(const StringRef Name);
|
|
|
|
StringRef getDfmtName(unsigned Id);
|
|
|
|
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
|
|
|
|
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
int64_t getUnifiedFormat(const StringRef Name);
|
|
|
|
StringRef getUnifiedFormatName(unsigned Id);
|
|
|
|
bool isValidUnifiedFormat(unsigned Val);
|
|
|
|
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
|
|
|
|
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
|
|
|
|
} // namespace MTBUFFormat
|
|
|
|
namespace SendMsg {
|
|
|
|
LLVM_READONLY
|
|
int64_t getMsgId(const StringRef Name);
|
|
|
|
LLVM_READONLY
|
|
int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
|
|
|
|
LLVM_READNONE
|
|
StringRef getMsgName(int64_t MsgId);
|
|
|
|
LLVM_READNONE
|
|
StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
|
|
|
|
LLVM_READNONE
|
|
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
|
|
|
|
LLVM_READNONE
|
|
bool isValidMsgOp(int64_t MsgId, int64_t OpId, bool Strict = true);
|
|
|
|
LLVM_READNONE
|
|
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, bool Strict = true);
|
|
|
|
LLVM_READNONE
|
|
bool msgRequiresOp(int64_t MsgId);
|
|
|
|
LLVM_READNONE
|
|
bool msgSupportsStream(int64_t MsgId, int64_t OpId);
|
|
|
|
void decodeMsg(unsigned Val,
|
|
uint16_t &MsgId,
|
|
uint16_t &OpId,
|
|
uint16_t &StreamId);
|
|
|
|
LLVM_READNONE
|
|
uint64_t encodeMsg(uint64_t MsgId,
|
|
uint64_t OpId,
|
|
uint64_t StreamId);
|
|
|
|
} // namespace SendMsg
|
|
|
|
|
|
unsigned getInitialPSInputAddr(const Function &F);
|
|
|
|
LLVM_READNONE
|
|
bool isShader(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isGraphics(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isCompute(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isEntryFunctionCC(CallingConv::ID CC);
|
|
|
|
// These functions are considered entrypoints into the current module, i.e. they
|
|
// are allowed to be called from outside the current module. This is different
|
|
// from isEntryFunctionCC, which is only true for functions that are entered by
|
|
// the hardware. Module entry points include all entry functions but also
|
|
// include functions that can be called from other functions inside or outside
|
|
// the current module. Module entry functions are allowed to allocate LDS.
|
|
LLVM_READNONE
|
|
bool isModuleEntryFunctionCC(CallingConv::ID CC);
|
|
|
|
// FIXME: Remove this when calling conventions cleaned up
|
|
LLVM_READNONE
|
|
inline bool isKernel(CallingConv::ID CC) {
|
|
switch (CC) {
|
|
case CallingConv::AMDGPU_KERNEL:
|
|
case CallingConv::SPIR_KERNEL:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool hasXNACK(const MCSubtargetInfo &STI);
|
|
bool hasSRAMECC(const MCSubtargetInfo &STI);
|
|
bool hasMIMG_R128(const MCSubtargetInfo &STI);
|
|
bool hasGFX10A16(const MCSubtargetInfo &STI);
|
|
bool hasG16(const MCSubtargetInfo &STI);
|
|
bool hasPackedD16(const MCSubtargetInfo &STI);
|
|
|
|
bool isSI(const MCSubtargetInfo &STI);
|
|
bool isCI(const MCSubtargetInfo &STI);
|
|
bool isVI(const MCSubtargetInfo &STI);
|
|
bool isGFX9(const MCSubtargetInfo &STI);
|
|
bool isGFX9Plus(const MCSubtargetInfo &STI);
|
|
bool isGFX10(const MCSubtargetInfo &STI);
|
|
bool isGFX10Plus(const MCSubtargetInfo &STI);
|
|
bool isGCN3Encoding(const MCSubtargetInfo &STI);
|
|
bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
|
|
bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
|
|
|
|
/// Is Reg - scalar register
|
|
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
|
|
|
|
/// Is there any intersection between registers
|
|
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
|
|
|
|
/// If \p Reg is a pseudo reg, return the correct hardware register given
|
|
/// \p STI otherwise return \p Reg.
|
|
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
|
|
|
|
/// Convert hardware register \p Reg to a pseudo register
|
|
LLVM_READNONE
|
|
unsigned mc2PseudoReg(unsigned Reg);
|
|
|
|
/// Can this operand also contain immediate values?
|
|
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Is this floating-point operand?
|
|
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Does this opearnd support only inlinable literals?
|
|
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Get the size in bits of a register from the register class \p RC.
|
|
unsigned getRegBitWidth(unsigned RCID);
|
|
|
|
/// Get the size in bits of a register from the register class \p RC.
|
|
unsigned getRegBitWidth(const MCRegisterClass &RC);
|
|
|
|
/// Get size of register operand
|
|
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
|
unsigned OpNo);
|
|
|
|
LLVM_READNONE
|
|
inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
|
|
switch (OpInfo.OperandType) {
|
|
case AMDGPU::OPERAND_REG_IMM_INT32:
|
|
case AMDGPU::OPERAND_REG_IMM_FP32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
|
|
return 4;
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT64:
|
|
case AMDGPU::OPERAND_REG_IMM_FP64:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
|
|
return 8;
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT16:
|
|
case AMDGPU::OPERAND_REG_IMM_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
|
|
case AMDGPU::OPERAND_REG_IMM_V2INT16:
|
|
case AMDGPU::OPERAND_REG_IMM_V2FP16:
|
|
return 2;
|
|
|
|
default:
|
|
llvm_unreachable("unhandled operand type");
|
|
}
|
|
}
|
|
|
|
LLVM_READNONE
|
|
inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
return getOperandSize(Desc.OpInfo[OpNo]);
|
|
}
|
|
|
|
/// Is this literal inlinable, and not one of the values intended for floating
|
|
/// point values.
|
|
LLVM_READNONE
|
|
inline bool isInlinableIntLiteral(int64_t Literal) {
|
|
return Literal >= -16 && Literal <= 64;
|
|
}
|
|
|
|
/// Is this literal inlinable
|
|
LLVM_READNONE
|
|
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableIntLiteralV216(int32_t Literal);
|
|
|
|
LLVM_READNONE
|
|
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
|
|
|
|
bool isArgPassedInSGPR(const Argument *Arg);
|
|
|
|
LLVM_READONLY
|
|
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
|
|
int64_t EncodedOffset);
|
|
|
|
LLVM_READONLY
|
|
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
|
|
int64_t EncodedOffset,
|
|
bool IsBuffer);
|
|
|
|
/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
|
|
/// offsets.
|
|
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
|
|
|
|
/// \returns The encoding that will be used for \p ByteOffset in the
|
|
/// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
|
|
/// S_LOAD instructions have a signed offset, on other subtargets it is
|
|
/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
|
|
Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
|
|
int64_t ByteOffset, bool IsBuffer);
|
|
|
|
/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
|
|
/// instruction. This is only useful on CI.s
|
|
Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
|
|
int64_t ByteOffset);
|
|
|
|
/// For FLAT segment the offset must be positive;
|
|
/// MSB is ignored and forced to zero.
|
|
///
|
|
/// \return The number of bits available for the offset field in flat
|
|
/// instructions.
|
|
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
|
|
|
|
/// \returns true if this offset is small enough to fit in the SMRD
|
|
/// offset field. \p ByteOffset should be the offset in bytes and
|
|
/// not the encoded offset.
|
|
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
|
|
|
|
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
|
|
const GCNSubtarget *Subtarget,
|
|
Align Alignment = Align(4));
|
|
|
|
/// \returns true if the intrinsic is divergent
|
|
bool isIntrinsicSourceOfDivergence(unsigned IntrID);
|
|
|
|
// Track defaults for fields in the MODE registser.
|
|
struct SIModeRegisterDefaults {
|
|
/// Floating point opcodes that support exception flag gathering quiet and
|
|
/// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
|
|
/// become IEEE 754- 2008 compliant due to signaling NaN propagation and
|
|
/// quieting.
|
|
bool IEEE : 1;
|
|
|
|
/// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
|
|
/// clamp NaN to zero; otherwise, pass NaN through.
|
|
bool DX10Clamp : 1;
|
|
|
|
/// If this is set, neither input or output denormals are flushed for most f32
|
|
/// instructions.
|
|
bool FP32InputDenormals : 1;
|
|
bool FP32OutputDenormals : 1;
|
|
|
|
/// If this is set, neither input or output denormals are flushed for both f64
|
|
/// and f16/v2f16 instructions.
|
|
bool FP64FP16InputDenormals : 1;
|
|
bool FP64FP16OutputDenormals : 1;
|
|
|
|
SIModeRegisterDefaults() :
|
|
IEEE(true),
|
|
DX10Clamp(true),
|
|
FP32InputDenormals(true),
|
|
FP32OutputDenormals(true),
|
|
FP64FP16InputDenormals(true),
|
|
FP64FP16OutputDenormals(true) {}
|
|
|
|
SIModeRegisterDefaults(const Function &F);
|
|
|
|
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
|
|
SIModeRegisterDefaults Mode;
|
|
Mode.IEEE = !AMDGPU::isShader(CC);
|
|
return Mode;
|
|
}
|
|
|
|
bool operator ==(const SIModeRegisterDefaults Other) const {
|
|
return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
|
|
FP32InputDenormals == Other.FP32InputDenormals &&
|
|
FP32OutputDenormals == Other.FP32OutputDenormals &&
|
|
FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
|
|
FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
|
|
}
|
|
|
|
bool allFP32Denormals() const {
|
|
return FP32InputDenormals && FP32OutputDenormals;
|
|
}
|
|
|
|
bool allFP64FP16Denormals() const {
|
|
return FP64FP16InputDenormals && FP64FP16OutputDenormals;
|
|
}
|
|
|
|
/// Get the encoding value for the FP_DENORM bits of the mode register for the
|
|
/// FP32 denormal mode.
|
|
uint32_t fpDenormModeSPValue() const {
|
|
if (FP32InputDenormals && FP32OutputDenormals)
|
|
return FP_DENORM_FLUSH_NONE;
|
|
if (FP32InputDenormals)
|
|
return FP_DENORM_FLUSH_OUT;
|
|
if (FP32OutputDenormals)
|
|
return FP_DENORM_FLUSH_IN;
|
|
return FP_DENORM_FLUSH_IN_FLUSH_OUT;
|
|
}
|
|
|
|
/// Get the encoding value for the FP_DENORM bits of the mode register for the
|
|
/// FP64/FP16 denormal mode.
|
|
uint32_t fpDenormModeDPValue() const {
|
|
if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
|
|
return FP_DENORM_FLUSH_NONE;
|
|
if (FP64FP16InputDenormals)
|
|
return FP_DENORM_FLUSH_OUT;
|
|
if (FP64FP16OutputDenormals)
|
|
return FP_DENORM_FLUSH_IN;
|
|
return FP_DENORM_FLUSH_IN_FLUSH_OUT;
|
|
}
|
|
|
|
/// Returns true if a flag is compatible if it's enabled in the callee, but
|
|
/// disabled in the caller.
|
|
static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
|
|
return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
|
|
}
|
|
|
|
// FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
|
|
// be able to override.
|
|
bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
|
|
if (DX10Clamp != CalleeMode.DX10Clamp)
|
|
return false;
|
|
if (IEEE != CalleeMode.IEEE)
|
|
return false;
|
|
|
|
// Allow inlining denormals enabled into denormals flushed functions.
|
|
return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
|
|
oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
|
|
oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
|
|
oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
|
|
}
|
|
};
|
|
|
|
} // end namespace AMDGPU
|
|
|
|
raw_ostream &operator<<(raw_ostream &OS,
|
|
const AMDGPU::IsaInfo::TargetIDSetting S);
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
|