950 lines
33 KiB
C++
950 lines
33 KiB
C++
//===- RegAllocPBQP.cpp ---- PBQP Register Allocator ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
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// register allocator for LLVM. This allocator works by constructing a PBQP
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// problem representing the register allocation problem under consideration,
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// solving this using a PBQP solver, and mapping the solution back to a
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// register assignment. If any variables are selected for spilling then spill
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// code is inserted and the process repeated.
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//
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// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
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// for register allocation. For more information on PBQP for register
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// allocation, see the following papers:
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//
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// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
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// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
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// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
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//
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// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
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// architectures. In Proceedings of the Joint Conference on Languages,
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// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
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// NY, USA, 139-148.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegAllocPBQP.h"
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#include "RegisterCoalescer.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/LiveStacks.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PBQP/Graph.h"
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#include "llvm/CodeGen/PBQP/Math.h"
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#include "llvm/CodeGen/PBQP/Solution.h"
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#include "llvm/CodeGen/PBQPRAConstraint.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/Spiller.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/FileSystem.h"
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#include "llvm/Support/Printable.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstddef>
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#include <limits>
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#include <map>
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#include <memory>
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#include <queue>
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#include <set>
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#include <sstream>
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#include <string>
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#include <system_error>
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#include <tuple>
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#include <utility>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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static RegisterRegAlloc
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RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
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createDefaultPBQPRegisterAllocator);
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static cl::opt<bool>
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PBQPCoalescing("pbqp-coalescing",
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cl::desc("Attempt coalescing during PBQP register allocation."),
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cl::init(false), cl::Hidden);
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#ifndef NDEBUG
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static cl::opt<bool>
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PBQPDumpGraphs("pbqp-dump-graphs",
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cl::desc("Dump graphs for each function/round in the compilation unit."),
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cl::init(false), cl::Hidden);
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#endif
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namespace {
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///
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/// PBQP based allocators solve the register allocation problem by mapping
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/// register allocation problems to Partitioned Boolean Quadratic
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/// Programming problems.
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class RegAllocPBQP : public MachineFunctionPass {
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public:
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static char ID;
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/// Construct a PBQP register allocator.
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RegAllocPBQP(char *cPassID = nullptr)
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: MachineFunctionPass(ID), customPassID(cPassID) {
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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}
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/// Return the pass name.
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StringRef getPassName() const override { return "PBQP Register Allocator"; }
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/// PBQP analysis usage.
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void getAnalysisUsage(AnalysisUsage &au) const override;
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/// Perform register allocation
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoPHIs);
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}
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MachineFunctionProperties getClearedProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::IsSSA);
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}
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private:
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using RegSet = std::set<Register>;
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char *customPassID;
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RegSet VRegsToAlloc, EmptyIntervalVRegs;
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/// Inst which is a def of an original reg and whose defs are already all
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/// dead after remat is saved in DeadRemats. The deletion of such inst is
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/// postponed till all the allocations are done, so its remat expr is
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/// always available for the remat of all the siblings of the original reg.
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SmallPtrSet<MachineInstr *, 32> DeadRemats;
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/// Finds the initial set of vreg intervals to allocate.
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void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
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/// Constructs an initial graph.
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void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
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/// Spill the given VReg.
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void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
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MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
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Spiller &VRegSpiller);
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/// Given a solved PBQP problem maps this solution back to a register
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/// assignment.
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bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
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const PBQP::Solution &Solution,
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VirtRegMap &VRM,
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Spiller &VRegSpiller);
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/// Postprocessing before final spilling. Sets basic block "live in"
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/// variables.
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void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
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VirtRegMap &VRM) const;
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void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
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};
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char RegAllocPBQP::ID = 0;
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/// Set spill costs for each node in the PBQP reg-alloc graph.
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class SpillCosts : public PBQPRAConstraint {
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public:
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void apply(PBQPRAGraph &G) override {
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LiveIntervals &LIS = G.getMetadata().LIS;
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// A minimum spill costs, so that register constraints can can be set
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// without normalization in the [0.0:MinSpillCost( interval.
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const PBQP::PBQPNum MinSpillCost = 10.0;
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for (auto NId : G.nodeIds()) {
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PBQP::PBQPNum SpillCost =
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LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight();
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if (SpillCost == 0.0)
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SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
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else
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SpillCost += MinSpillCost;
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PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
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NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
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G.setNodeCosts(NId, std::move(NodeCosts));
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}
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}
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};
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/// Add interference edges between overlapping vregs.
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class Interference : public PBQPRAConstraint {
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private:
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using AllowedRegVecPtr = const PBQP::RegAlloc::AllowedRegVector *;
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using IKey = std::pair<AllowedRegVecPtr, AllowedRegVecPtr>;
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using IMatrixCache = DenseMap<IKey, PBQPRAGraph::MatrixPtr>;
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using DisjointAllowedRegsCache = DenseSet<IKey>;
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using IEdgeKey = std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId>;
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using IEdgeCache = DenseSet<IEdgeKey>;
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bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
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PBQPRAGraph::NodeId MId,
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const DisjointAllowedRegsCache &D) const {
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const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
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const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
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if (NRegs == MRegs)
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return false;
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if (NRegs < MRegs)
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return D.contains(IKey(NRegs, MRegs));
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return D.contains(IKey(MRegs, NRegs));
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}
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void setDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
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PBQPRAGraph::NodeId MId,
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DisjointAllowedRegsCache &D) {
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const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
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const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
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assert(NRegs != MRegs && "AllowedRegs can not be disjoint with itself");
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if (NRegs < MRegs)
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D.insert(IKey(NRegs, MRegs));
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else
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D.insert(IKey(MRegs, NRegs));
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}
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// Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
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// for the fast interference graph construction algorithm. The last is there
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// to save us from looking up node ids via the VRegToNode map in the graph
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// metadata.
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using IntervalInfo =
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std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>;
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static SlotIndex getStartPoint(const IntervalInfo &I) {
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return std::get<0>(I)->segments[std::get<1>(I)].start;
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}
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static SlotIndex getEndPoint(const IntervalInfo &I) {
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return std::get<0>(I)->segments[std::get<1>(I)].end;
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}
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static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
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return std::get<2>(I);
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}
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static bool lowestStartPoint(const IntervalInfo &I1,
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const IntervalInfo &I2) {
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// Condition reversed because priority queue has the *highest* element at
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// the front, rather than the lowest.
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return getStartPoint(I1) > getStartPoint(I2);
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}
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static bool lowestEndPoint(const IntervalInfo &I1,
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const IntervalInfo &I2) {
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SlotIndex E1 = getEndPoint(I1);
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SlotIndex E2 = getEndPoint(I2);
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if (E1 < E2)
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return true;
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if (E1 > E2)
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return false;
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// If two intervals end at the same point, we need a way to break the tie or
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// the set will assume they're actually equal and refuse to insert a
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// "duplicate". Just compare the vregs - fast and guaranteed unique.
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return std::get<0>(I1)->reg() < std::get<0>(I2)->reg();
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}
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static bool isAtLastSegment(const IntervalInfo &I) {
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return std::get<1>(I) == std::get<0>(I)->size() - 1;
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}
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static IntervalInfo nextSegment(const IntervalInfo &I) {
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return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
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}
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public:
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void apply(PBQPRAGraph &G) override {
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// The following is loosely based on the linear scan algorithm introduced in
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// "Linear Scan Register Allocation" by Poletto and Sarkar. This version
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// isn't linear, because the size of the active set isn't bound by the
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// number of registers, but rather the size of the largest clique in the
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// graph. Still, we expect this to be better than N^2.
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LiveIntervals &LIS = G.getMetadata().LIS;
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// Interferenc matrices are incredibly regular - they're only a function of
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// the allowed sets, so we cache them to avoid the overhead of constructing
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// and uniquing them.
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IMatrixCache C;
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// Finding an edge is expensive in the worst case (O(max_clique(G))). So
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// cache locally edges we have already seen.
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IEdgeCache EC;
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// Cache known disjoint allowed registers pairs
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DisjointAllowedRegsCache D;
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using IntervalSet = std::set<IntervalInfo, decltype(&lowestEndPoint)>;
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using IntervalQueue =
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std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
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decltype(&lowestStartPoint)>;
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IntervalSet Active(lowestEndPoint);
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IntervalQueue Inactive(lowestStartPoint);
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// Start by building the inactive set.
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for (auto NId : G.nodeIds()) {
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Register VReg = G.getNodeMetadata(NId).getVReg();
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LiveInterval &LI = LIS.getInterval(VReg);
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assert(!LI.empty() && "PBQP graph contains node for empty interval");
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Inactive.push(std::make_tuple(&LI, 0, NId));
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}
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while (!Inactive.empty()) {
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// Tentatively grab the "next" interval - this choice may be overriden
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// below.
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IntervalInfo Cur = Inactive.top();
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// Retire any active intervals that end before Cur starts.
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IntervalSet::iterator RetireItr = Active.begin();
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while (RetireItr != Active.end() &&
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(getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
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// If this interval has subsequent segments, add the next one to the
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// inactive list.
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if (!isAtLastSegment(*RetireItr))
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Inactive.push(nextSegment(*RetireItr));
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++RetireItr;
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}
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Active.erase(Active.begin(), RetireItr);
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// One of the newly retired segments may actually start before the
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// Cur segment, so re-grab the front of the inactive list.
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Cur = Inactive.top();
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Inactive.pop();
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// At this point we know that Cur overlaps all active intervals. Add the
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// interference edges.
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PBQP::GraphBase::NodeId NId = getNodeId(Cur);
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for (const auto &A : Active) {
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PBQP::GraphBase::NodeId MId = getNodeId(A);
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// Do not add an edge when the nodes' allowed registers do not
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// intersect: there is obviously no interference.
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if (haveDisjointAllowedRegs(G, NId, MId, D))
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continue;
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// Check that we haven't already added this edge
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IEdgeKey EK(std::min(NId, MId), std::max(NId, MId));
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if (EC.count(EK))
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continue;
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// This is a new edge - add it to the graph.
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if (!createInterferenceEdge(G, NId, MId, C))
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setDisjointAllowedRegs(G, NId, MId, D);
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else
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EC.insert(EK);
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}
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// Finally, add Cur to the Active set.
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Active.insert(Cur);
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}
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}
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private:
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// Create an Interference edge and add it to the graph, unless it is
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// a null matrix, meaning the nodes' allowed registers do not have any
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// interference. This case occurs frequently between integer and floating
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// point registers for example.
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// return true iff both nodes interferes.
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bool createInterferenceEdge(PBQPRAGraph &G,
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PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
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IMatrixCache &C) {
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const TargetRegisterInfo &TRI =
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*G.getMetadata().MF.getSubtarget().getRegisterInfo();
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const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
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const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
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// Try looking the edge costs up in the IMatrixCache first.
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IKey K(&NRegs, &MRegs);
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IMatrixCache::iterator I = C.find(K);
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if (I != C.end()) {
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G.addEdgeBypassingCostAllocator(NId, MId, I->second);
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return true;
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}
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PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
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bool NodesInterfere = false;
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for (unsigned I = 0; I != NRegs.size(); ++I) {
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MCRegister PRegN = NRegs[I];
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for (unsigned J = 0; J != MRegs.size(); ++J) {
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MCRegister PRegM = MRegs[J];
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if (TRI.regsOverlap(PRegN, PRegM)) {
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M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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NodesInterfere = true;
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}
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}
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}
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if (!NodesInterfere)
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return false;
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PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
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C[K] = G.getEdgeCostsPtr(EId);
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return true;
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}
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};
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class Coalescing : public PBQPRAConstraint {
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public:
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void apply(PBQPRAGraph &G) override {
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MachineFunction &MF = G.getMetadata().MF;
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MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
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CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
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// Scan the machine function and add a coalescing cost whenever CoalescerPair
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// gives the Ok.
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for (const auto &MBB : MF) {
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for (const auto &MI : MBB) {
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// Skip not-coalescable or already coalesced copies.
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if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
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continue;
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Register DstReg = CP.getDstReg();
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Register SrcReg = CP.getSrcReg();
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PBQP::PBQPNum CBenefit = MBFI.getBlockFreqRelativeToEntryBlock(&MBB);
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if (CP.isPhys()) {
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if (!MF.getRegInfo().isAllocatable(DstReg))
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continue;
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PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
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const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
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G.getNodeMetadata(NId).getAllowedRegs();
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unsigned PRegOpt = 0;
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while (PRegOpt < Allowed.size() && Allowed[PRegOpt].id() != DstReg)
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++PRegOpt;
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if (PRegOpt < Allowed.size()) {
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PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
|
|
NewCosts[PRegOpt + 1] -= CBenefit;
|
|
G.setNodeCosts(NId, std::move(NewCosts));
|
|
}
|
|
} else {
|
|
PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
|
|
PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
|
|
const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
|
|
&G.getNodeMetadata(N1Id).getAllowedRegs();
|
|
const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
|
|
&G.getNodeMetadata(N2Id).getAllowedRegs();
|
|
|
|
PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
|
|
if (EId == G.invalidEdgeId()) {
|
|
PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
|
|
Allowed2->size() + 1, 0);
|
|
addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
|
|
G.addEdge(N1Id, N2Id, std::move(Costs));
|
|
} else {
|
|
if (G.getEdgeNode1Id(EId) == N2Id) {
|
|
std::swap(N1Id, N2Id);
|
|
std::swap(Allowed1, Allowed2);
|
|
}
|
|
PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
|
|
addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
|
|
G.updateEdgeCosts(EId, std::move(Costs));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
private:
|
|
void addVirtRegCoalesce(
|
|
PBQPRAGraph::RawMatrix &CostMat,
|
|
const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
|
|
const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
|
|
PBQP::PBQPNum Benefit) {
|
|
assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
|
|
assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
|
|
for (unsigned I = 0; I != Allowed1.size(); ++I) {
|
|
MCRegister PReg1 = Allowed1[I];
|
|
for (unsigned J = 0; J != Allowed2.size(); ++J) {
|
|
MCRegister PReg2 = Allowed2[J];
|
|
if (PReg1 == PReg2)
|
|
CostMat[I + 1][J + 1] -= Benefit;
|
|
}
|
|
}
|
|
}
|
|
};
|
|
|
|
/// PBQP-specific implementation of weight normalization.
|
|
class PBQPVirtRegAuxInfo final : public VirtRegAuxInfo {
|
|
float normalize(float UseDefFreq, unsigned Size, unsigned NumInstr) override {
|
|
// All intervals have a spill weight that is mostly proportional to the
|
|
// number of uses, with uses in loops having a bigger weight.
|
|
return NumInstr * VirtRegAuxInfo::normalize(UseDefFreq, Size, 1);
|
|
}
|
|
|
|
public:
|
|
PBQPVirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
|
|
const MachineLoopInfo &Loops,
|
|
const MachineBlockFrequencyInfo &MBFI)
|
|
: VirtRegAuxInfo(MF, LIS, VRM, Loops, MBFI) {}
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
// Out-of-line destructor/anchor for PBQPRAConstraint.
|
|
PBQPRAConstraint::~PBQPRAConstraint() = default;
|
|
|
|
void PBQPRAConstraint::anchor() {}
|
|
|
|
void PBQPRAConstraintList::anchor() {}
|
|
|
|
void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
|
|
au.setPreservesCFG();
|
|
au.addRequired<AAResultsWrapperPass>();
|
|
au.addPreserved<AAResultsWrapperPass>();
|
|
au.addRequired<SlotIndexes>();
|
|
au.addPreserved<SlotIndexes>();
|
|
au.addRequired<LiveIntervals>();
|
|
au.addPreserved<LiveIntervals>();
|
|
//au.addRequiredID(SplitCriticalEdgesID);
|
|
if (customPassID)
|
|
au.addRequiredID(*customPassID);
|
|
au.addRequired<LiveStacks>();
|
|
au.addPreserved<LiveStacks>();
|
|
au.addRequired<MachineBlockFrequencyInfo>();
|
|
au.addPreserved<MachineBlockFrequencyInfo>();
|
|
au.addRequired<MachineLoopInfo>();
|
|
au.addPreserved<MachineLoopInfo>();
|
|
au.addRequired<MachineDominatorTree>();
|
|
au.addPreserved<MachineDominatorTree>();
|
|
au.addRequired<VirtRegMap>();
|
|
au.addPreserved<VirtRegMap>();
|
|
MachineFunctionPass::getAnalysisUsage(au);
|
|
}
|
|
|
|
void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
|
|
LiveIntervals &LIS) {
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
// Iterate over all live ranges.
|
|
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
|
|
Register Reg = Register::index2VirtReg(I);
|
|
if (MRI.reg_nodbg_empty(Reg))
|
|
continue;
|
|
VRegsToAlloc.insert(Reg);
|
|
}
|
|
}
|
|
|
|
static bool isACalleeSavedRegister(MCRegister Reg,
|
|
const TargetRegisterInfo &TRI,
|
|
const MachineFunction &MF) {
|
|
const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs();
|
|
for (unsigned i = 0; CSR[i] != 0; ++i)
|
|
if (TRI.regsOverlap(Reg, CSR[i]))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
|
|
Spiller &VRegSpiller) {
|
|
MachineFunction &MF = G.getMetadata().MF;
|
|
|
|
LiveIntervals &LIS = G.getMetadata().LIS;
|
|
const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
|
|
const TargetRegisterInfo &TRI =
|
|
*G.getMetadata().MF.getSubtarget().getRegisterInfo();
|
|
|
|
std::vector<Register> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
|
|
|
|
std::map<Register, std::vector<MCRegister>> VRegAllowedMap;
|
|
|
|
while (!Worklist.empty()) {
|
|
Register VReg = Worklist.back();
|
|
Worklist.pop_back();
|
|
|
|
LiveInterval &VRegLI = LIS.getInterval(VReg);
|
|
|
|
// If this is an empty interval move it to the EmptyIntervalVRegs set then
|
|
// continue.
|
|
if (VRegLI.empty()) {
|
|
EmptyIntervalVRegs.insert(VRegLI.reg());
|
|
VRegsToAlloc.erase(VRegLI.reg());
|
|
continue;
|
|
}
|
|
|
|
const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
|
|
|
|
// Record any overlaps with regmask operands.
|
|
BitVector RegMaskOverlaps;
|
|
LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
|
|
|
|
// Compute an initial allowed set for the current vreg.
|
|
std::vector<MCRegister> VRegAllowed;
|
|
ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
|
|
for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
|
|
MCRegister PReg(RawPRegOrder[I]);
|
|
if (MRI.isReserved(PReg))
|
|
continue;
|
|
|
|
// vregLI crosses a regmask operand that clobbers preg.
|
|
if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
|
|
continue;
|
|
|
|
// vregLI overlaps fixed regunit interference.
|
|
bool Interference = false;
|
|
for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
|
|
if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
|
|
Interference = true;
|
|
break;
|
|
}
|
|
}
|
|
if (Interference)
|
|
continue;
|
|
|
|
// preg is usable for this virtual register.
|
|
VRegAllowed.push_back(PReg);
|
|
}
|
|
|
|
// Check for vregs that have no allowed registers. These should be
|
|
// pre-spilled and the new vregs added to the worklist.
|
|
if (VRegAllowed.empty()) {
|
|
SmallVector<Register, 8> NewVRegs;
|
|
spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
|
|
llvm::append_range(Worklist, NewVRegs);
|
|
continue;
|
|
}
|
|
|
|
VRegAllowedMap[VReg.id()] = std::move(VRegAllowed);
|
|
}
|
|
|
|
for (auto &KV : VRegAllowedMap) {
|
|
auto VReg = KV.first;
|
|
|
|
// Move empty intervals to the EmptyIntervalVReg set.
|
|
if (LIS.getInterval(VReg).empty()) {
|
|
EmptyIntervalVRegs.insert(VReg);
|
|
VRegsToAlloc.erase(VReg);
|
|
continue;
|
|
}
|
|
|
|
auto &VRegAllowed = KV.second;
|
|
|
|
PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
|
|
|
|
// Tweak cost of callee saved registers, as using then force spilling and
|
|
// restoring them. This would only happen in the prologue / epilogue though.
|
|
for (unsigned i = 0; i != VRegAllowed.size(); ++i)
|
|
if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
|
|
NodeCosts[1 + i] += 1.0;
|
|
|
|
PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
|
|
G.getNodeMetadata(NId).setVReg(VReg);
|
|
G.getNodeMetadata(NId).setAllowedRegs(
|
|
G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
|
|
G.getMetadata().setNodeIdForVReg(VReg, NId);
|
|
}
|
|
}
|
|
|
|
void RegAllocPBQP::spillVReg(Register VReg,
|
|
SmallVectorImpl<Register> &NewIntervals,
|
|
MachineFunction &MF, LiveIntervals &LIS,
|
|
VirtRegMap &VRM, Spiller &VRegSpiller) {
|
|
VRegsToAlloc.erase(VReg);
|
|
LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
|
|
nullptr, &DeadRemats);
|
|
VRegSpiller.spill(LRE);
|
|
|
|
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
|
(void)TRI;
|
|
LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: "
|
|
<< LRE.getParent().weight() << ", New vregs: ");
|
|
|
|
// Copy any newly inserted live intervals into the list of regs to
|
|
// allocate.
|
|
for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
|
|
I != E; ++I) {
|
|
const LiveInterval &LI = LIS.getInterval(*I);
|
|
assert(!LI.empty() && "Empty spill range.");
|
|
LLVM_DEBUG(dbgs() << printReg(LI.reg(), &TRI) << " ");
|
|
VRegsToAlloc.insert(LI.reg());
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << ")\n");
|
|
}
|
|
|
|
bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
|
|
const PBQP::Solution &Solution,
|
|
VirtRegMap &VRM,
|
|
Spiller &VRegSpiller) {
|
|
MachineFunction &MF = G.getMetadata().MF;
|
|
LiveIntervals &LIS = G.getMetadata().LIS;
|
|
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
|
(void)TRI;
|
|
|
|
// Set to true if we have any spills
|
|
bool AnotherRoundNeeded = false;
|
|
|
|
// Clear the existing allocation.
|
|
VRM.clearAllVirt();
|
|
|
|
// Iterate over the nodes mapping the PBQP solution to a register
|
|
// assignment.
|
|
for (auto NId : G.nodeIds()) {
|
|
Register VReg = G.getNodeMetadata(NId).getVReg();
|
|
unsigned AllocOpt = Solution.getSelection(NId);
|
|
|
|
if (AllocOpt != PBQP::RegAlloc::getSpillOptionIdx()) {
|
|
MCRegister PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOpt - 1];
|
|
LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> "
|
|
<< TRI.getName(PReg) << "\n");
|
|
assert(PReg != 0 && "Invalid preg selected.");
|
|
VRM.assignVirt2Phys(VReg, PReg);
|
|
} else {
|
|
// Spill VReg. If this introduces new intervals we'll need another round
|
|
// of allocation.
|
|
SmallVector<Register, 8> NewVRegs;
|
|
spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
|
|
AnotherRoundNeeded |= !NewVRegs.empty();
|
|
}
|
|
}
|
|
|
|
return !AnotherRoundNeeded;
|
|
}
|
|
|
|
void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
|
|
LiveIntervals &LIS,
|
|
VirtRegMap &VRM) const {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
// First allocate registers for the empty intervals.
|
|
for (RegSet::const_iterator
|
|
I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
|
|
I != E; ++I) {
|
|
LiveInterval &LI = LIS.getInterval(*I);
|
|
|
|
Register PReg = MRI.getSimpleHint(LI.reg());
|
|
|
|
if (PReg == 0) {
|
|
const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg());
|
|
const ArrayRef<MCPhysReg> RawPRegOrder = RC.getRawAllocationOrder(MF);
|
|
for (MCRegister CandidateReg : RawPRegOrder) {
|
|
if (!VRM.getRegInfo().isReserved(CandidateReg)) {
|
|
PReg = CandidateReg;
|
|
break;
|
|
}
|
|
}
|
|
assert(PReg &&
|
|
"No un-reserved physical registers in this register class");
|
|
}
|
|
|
|
VRM.assignVirt2Phys(LI.reg(), PReg);
|
|
}
|
|
}
|
|
|
|
void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
|
|
VRegSpiller.postOptimization();
|
|
/// Remove dead defs because of rematerialization.
|
|
for (auto DeadInst : DeadRemats) {
|
|
LIS.RemoveMachineInstrFromMaps(*DeadInst);
|
|
DeadInst->eraseFromParent();
|
|
}
|
|
DeadRemats.clear();
|
|
}
|
|
|
|
bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
|
|
LiveIntervals &LIS = getAnalysis<LiveIntervals>();
|
|
MachineBlockFrequencyInfo &MBFI =
|
|
getAnalysis<MachineBlockFrequencyInfo>();
|
|
|
|
VirtRegMap &VRM = getAnalysis<VirtRegMap>();
|
|
|
|
PBQPVirtRegAuxInfo VRAI(MF, LIS, VRM, getAnalysis<MachineLoopInfo>(), MBFI);
|
|
VRAI.calculateSpillWeightsAndHints();
|
|
|
|
std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
|
|
|
|
MF.getRegInfo().freezeReservedRegs(MF);
|
|
|
|
LLVM_DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
|
|
|
|
// Allocator main loop:
|
|
//
|
|
// * Map current regalloc problem to a PBQP problem
|
|
// * Solve the PBQP problem
|
|
// * Map the solution back to a register allocation
|
|
// * Spill if necessary
|
|
//
|
|
// This process is continued till no more spills are generated.
|
|
|
|
// Find the vreg intervals in need of allocation.
|
|
findVRegIntervalsToAlloc(MF, LIS);
|
|
|
|
#ifndef NDEBUG
|
|
const Function &F = MF.getFunction();
|
|
std::string FullyQualifiedName =
|
|
F.getParent()->getModuleIdentifier() + "." + F.getName().str();
|
|
#endif
|
|
|
|
// If there are non-empty intervals allocate them using pbqp.
|
|
if (!VRegsToAlloc.empty()) {
|
|
const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
|
|
std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
|
|
std::make_unique<PBQPRAConstraintList>();
|
|
ConstraintsRoot->addConstraint(std::make_unique<SpillCosts>());
|
|
ConstraintsRoot->addConstraint(std::make_unique<Interference>());
|
|
if (PBQPCoalescing)
|
|
ConstraintsRoot->addConstraint(std::make_unique<Coalescing>());
|
|
ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
|
|
|
|
bool PBQPAllocComplete = false;
|
|
unsigned Round = 0;
|
|
|
|
while (!PBQPAllocComplete) {
|
|
LLVM_DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
|
|
|
|
PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
|
|
initializeGraph(G, VRM, *VRegSpiller);
|
|
ConstraintsRoot->apply(G);
|
|
|
|
#ifndef NDEBUG
|
|
if (PBQPDumpGraphs) {
|
|
std::ostringstream RS;
|
|
RS << Round;
|
|
std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
|
|
".pbqpgraph";
|
|
std::error_code EC;
|
|
raw_fd_ostream OS(GraphFileName, EC, sys::fs::OF_Text);
|
|
LLVM_DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
|
|
<< GraphFileName << "\"\n");
|
|
G.dump(OS);
|
|
}
|
|
#endif
|
|
|
|
PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
|
|
PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
|
|
++Round;
|
|
}
|
|
}
|
|
|
|
// Finalise allocation, allocate empty ranges.
|
|
finalizeAlloc(MF, LIS, VRM);
|
|
postOptimization(*VRegSpiller, LIS);
|
|
VRegsToAlloc.clear();
|
|
EmptyIntervalVRegs.clear();
|
|
|
|
LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
|
|
|
|
return true;
|
|
}
|
|
|
|
/// Create Printable object for node and register info.
|
|
static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
|
|
const PBQP::RegAlloc::PBQPRAGraph &G) {
|
|
return Printable([NId, &G](raw_ostream &OS) {
|
|
const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
|
|
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
|
|
Register VReg = G.getNodeMetadata(NId).getVReg();
|
|
const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
|
|
OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')';
|
|
});
|
|
}
|
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
|
LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
|
|
for (auto NId : nodeIds()) {
|
|
const Vector &Costs = getNodeCosts(NId);
|
|
assert(Costs.getLength() != 0 && "Empty vector in graph.");
|
|
OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
|
|
}
|
|
OS << '\n';
|
|
|
|
for (auto EId : edgeIds()) {
|
|
NodeId N1Id = getEdgeNode1Id(EId);
|
|
NodeId N2Id = getEdgeNode2Id(EId);
|
|
assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
|
|
const Matrix &M = getEdgeCosts(EId);
|
|
assert(M.getRows() != 0 && "No rows in matrix.");
|
|
assert(M.getCols() != 0 && "No cols in matrix.");
|
|
OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
|
|
OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
|
|
OS << M << '\n';
|
|
}
|
|
}
|
|
|
|
LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const {
|
|
dump(dbgs());
|
|
}
|
|
#endif
|
|
|
|
void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const {
|
|
OS << "graph {\n";
|
|
for (auto NId : nodeIds()) {
|
|
OS << " node" << NId << " [ label=\""
|
|
<< PrintNodeInfo(NId, *this) << "\\n"
|
|
<< getNodeCosts(NId) << "\" ]\n";
|
|
}
|
|
|
|
OS << " edge [ len=" << nodeIds().size() << " ]\n";
|
|
for (auto EId : edgeIds()) {
|
|
OS << " node" << getEdgeNode1Id(EId)
|
|
<< " -- node" << getEdgeNode2Id(EId)
|
|
<< " [ label=\"";
|
|
const Matrix &EdgeCosts = getEdgeCosts(EId);
|
|
for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
|
|
OS << EdgeCosts.getRowAsVector(i) << "\\n";
|
|
}
|
|
OS << "\" ]\n";
|
|
}
|
|
OS << "}\n";
|
|
}
|
|
|
|
FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
|
|
return new RegAllocPBQP(customPassID);
|
|
}
|
|
|
|
FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
|
|
return createPBQPRegisterAllocator();
|
|
}
|