172 lines
6.8 KiB
C++
172 lines
6.8 KiB
C++
//===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MCInstrAnalysis class which the MCTargetDescs can
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// derive from to give additional information to MC.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINSTRANALYSIS_H
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#define LLVM_MC_MCINSTRANALYSIS_H
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include <cstdint>
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namespace llvm {
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class MCRegisterInfo;
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class Triple;
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class MCInstrAnalysis {
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protected:
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friend class Target;
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const MCInstrInfo *Info;
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public:
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MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
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virtual ~MCInstrAnalysis() = default;
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virtual bool isBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isBranch();
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}
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virtual bool isConditionalBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isConditionalBranch();
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}
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virtual bool isUnconditionalBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isUnconditionalBranch();
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}
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virtual bool isIndirectBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isIndirectBranch();
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}
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virtual bool isCall(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isCall();
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}
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virtual bool isReturn(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isReturn();
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}
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virtual bool isTerminator(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isTerminator();
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}
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/// Returns true if at least one of the register writes performed by
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/// \param Inst implicitly clears the upper portion of all super-registers.
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///
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/// Example: on X86-64, a write to EAX implicitly clears the upper half of
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/// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
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/// instruction implicitly clears the upper portion of the correspondent
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/// YMM register.
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///
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/// This method also updates an APInt which is used as mask of register
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/// writes. There is one bit for every explicit/implicit write performed by
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/// the instruction. If a write implicitly clears its super-registers, then
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/// the corresponding bit is set (vic. the corresponding bit is cleared).
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///
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/// The first bits in the APint are related to explicit writes. The remaining
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/// bits are related to implicit writes. The sequence of writes follows the
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/// machine operand sequence. For implicit writes, the sequence is defined by
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/// the MCInstrDesc.
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///
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/// The assumption is that the bit-width of the APInt is correctly set by
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/// the caller. The default implementation conservatively assumes that none of
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/// the writes clears the upper portion of a super-register.
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virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
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const MCInst &Inst,
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APInt &Writes) const;
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/// Returns true if MI is a dependency breaking zero-idiom for the given
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/// subtarget.
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///
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/// Mask is used to identify input operands that have their dependency
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/// broken. Each bit of the mask is associated with a specific input operand.
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/// Bits associated with explicit input operands are laid out first in the
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/// mask; implicit operands come after explicit operands.
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///
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/// Dependencies are broken only for operands that have their corresponding bit
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/// set. Operands that have their bit cleared, or that don't have a
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/// corresponding bit in the mask don't have their dependency broken. Note
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/// that Mask may not be big enough to describe all operands. The assumption
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/// for operands that don't have a correspondent bit in the mask is that those
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/// are still data dependent.
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///
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/// The only exception to the rule is for when Mask has all zeroes.
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/// A zero mask means: dependencies are broken for all explicit register
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/// operands.
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virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask,
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unsigned CPUID) const {
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return false;
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}
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/// Returns true if MI is a dependency breaking instruction for the
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/// subtarget associated with CPUID .
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///
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/// The value computed by a dependency breaking instruction is not dependent
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/// on the inputs. An example of dependency breaking instruction on X86 is
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/// `XOR %eax, %eax`.
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///
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/// If MI is a dependency breaking instruction for subtarget CPUID, then Mask
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/// can be inspected to identify independent operands.
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///
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/// Essentially, each bit of the mask corresponds to an input operand.
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/// Explicit operands are laid out first in the mask; implicit operands follow
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/// explicit operands. Bits are set for operands that are independent.
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///
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/// Note that the number of bits in Mask may not be equivalent to the sum of
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/// explicit and implicit operands in MI. Operands that don't have a
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/// corresponding bit in Mask are assumed "not independente".
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///
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/// The only exception is for when Mask is all zeroes. That means: explicit
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/// input operands of MI are independent.
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virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask,
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unsigned CPUID) const {
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return isZeroIdiom(MI, Mask, CPUID);
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}
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/// Returns true if MI is a candidate for move elimination.
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///
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/// Different subtargets may apply different constraints to optimizable
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/// register moves. For example, on most X86 subtargets, a candidate for move
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/// elimination cannot specify the same register for both source and
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/// destination.
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virtual bool isOptimizableRegisterMove(const MCInst &MI,
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unsigned CPUID) const {
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return false;
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}
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/// Given a branch instruction try to get the address the branch
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/// targets. Return true on success, and the address in Target.
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virtual bool
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evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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uint64_t &Target) const;
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/// Given an instruction tries to get the address of a memory operand. Returns
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/// the address on success.
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virtual Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
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uint64_t Addr,
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uint64_t Size) const;
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/// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
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virtual std::vector<std::pair<uint64_t, uint64_t>>
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findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
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uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
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return {};
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}
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};
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} // end namespace llvm
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#endif // LLVM_MC_MCINSTRANALYSIS_H
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