157 lines
5.6 KiB
C++
157 lines
5.6 KiB
C++
//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains descriptions of the various Vector Predication intrinsics.
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// This is used as a central place for enumerating the different instructions
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// and should eventually be the place to put comments about the instructions.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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// Provide definitions of macros so that users of this file do not have to
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// define everything to use it...
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//
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// Register a VP intrinsic and begin its property scope.
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// All VP intrinsic scopes are top level, ie it is illegal to place a
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// BEGIN_REGISTER_VP_INTRINSIC within a VP intrinsic scope.
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// \p VPID The VP intrinsic id.
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// \p MASKPOS The mask operand position.
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// \p EVLPOS The explicit vector length operand position.
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#ifndef BEGIN_REGISTER_VP_INTRINSIC
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#define BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS)
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#endif
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// End the property scope of a VP intrinsic.
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#ifndef END_REGISTER_VP_INTRINSIC
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#define END_REGISTER_VP_INTRINSIC(VPID)
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#endif
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// Register a new VP SDNode and begin its property scope.
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// When the SDNode scope is nested within a VP intrinsic scope, it is implicitly registered as the canonical SDNode for this VP intrinsic.
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// There is one VP intrinsic that maps directly to one SDNode that goes by the
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// same name. Since the operands are also the same, we open the property
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// scopes for both the VPIntrinsic and the SDNode at once.
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// \p SDOPC The SelectionDAG Node id (eg VP_ADD).
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// \p LEGALPOS The operand position of the SDNode that is used for legalizing
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// this SDNode. This can be `-1`, in which case the return type of
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// the SDNode is used.
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// \p TDNAME The name of the TableGen definition of this SDNode.
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// \p MASKPOS The mask operand position.
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// \p EVLPOS The explicit vector length operand position.
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#ifndef BEGIN_REGISTER_VP_SDNODE
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#define BEGIN_REGISTER_VP_SDNODE(SDOPC, LEGALPOS, TDNAME, MASKPOS, EVLPOS)
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#endif
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// End the property scope of a new VP SDNode.
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#ifndef END_REGISTER_VP_SDNODE
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#define END_REGISTER_VP_SDNODE(SDOPC)
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#endif
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// Helper macros for the common "1:1 - Intrinsic : SDNode" case.
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//
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// There is one VP intrinsic that maps directly to one SDNode that goes by the
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// same name. Since the operands are also the same, we open the property
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// scopes for both the VPIntrinsic and the SDNode at once.
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//
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// \p INTRIN The canonical name (eg `vp_add`, which at the same time is the
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// name of the intrinsic and the TableGen def of the SDNode).
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// \p MASKPOS The mask operand position.
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// \p EVLPOS The explicit vector length operand position.
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// \p SDOPC The SelectionDAG Node id (eg VP_ADD).
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// \p LEGALPOS The operand position of the SDNode that is used for legalizing
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// this SDNode. This can be `-1`, in which case the return type of
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// the SDNode is used.
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#define BEGIN_REGISTER_VP(INTRIN, MASKPOS, EVLPOS, SDOPC, LEGALPOS) \
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BEGIN_REGISTER_VP_INTRINSIC(INTRIN, MASKPOS, EVLPOS) \
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BEGIN_REGISTER_VP_SDNODE(SDOPC, LEGALPOS, INTRIN, MASKPOS, EVLPOS)
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#define END_REGISTER_VP(INTRIN, SDOPC) \
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END_REGISTER_VP_INTRINSIC(INTRIN) \
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END_REGISTER_VP_SDNODE(SDOPC)
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// The following macros attach properties to the scope they are placed in. This
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// assigns the property to the VP Intrinsic and/or SDNode that belongs to the
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// scope.
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//
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// Property Macros {
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// The intrinsic and/or SDNode has the same function as this LLVM IR Opcode.
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// \p OPC The standard IR opcode.
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#ifndef HANDLE_VP_TO_OPC
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#define HANDLE_VP_TO_OPC(OPC)
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#endif
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/// } Property Macros
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///// Integer Arithmetic {
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// Specialized helper macro for integer binary operators (%x, %y, %mask, %evl).
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#ifdef HELPER_REGISTER_BINARY_INT_VP
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#error "The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!"
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#endif
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#define HELPER_REGISTER_BINARY_INT_VP(INTRIN, SDOPC, OPC) \
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BEGIN_REGISTER_VP(INTRIN, 2, 3, SDOPC, -1) \
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HANDLE_VP_TO_OPC(OPC) \
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END_REGISTER_VP(INTRIN, SDOPC)
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// llvm.vp.add(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add)
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// llvm.vp.and(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And)
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// llvm.vp.ashr(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_ASHR, AShr)
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// llvm.vp.lshr(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_LSHR, LShr)
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// llvm.vp.mul(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul)
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// llvm.vp.or(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or)
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// llvm.vp.sdiv(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv)
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// llvm.vp.shl(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl)
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// llvm.vp.srem(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem)
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// llvm.vp.sub(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub)
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// llvm.vp.udiv(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv)
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// llvm.vp.urem(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem)
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// llvm.vp.xor(x,y,mask,vlen)
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HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor)
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#undef HELPER_REGISTER_BINARY_INT_VP
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///// } Integer Arithmetic
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#undef BEGIN_REGISTER_VP
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#undef BEGIN_REGISTER_VP_INTRINSIC
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#undef BEGIN_REGISTER_VP_SDNODE
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#undef END_REGISTER_VP
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#undef END_REGISTER_VP_INTRINSIC
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#undef END_REGISTER_VP_SDNODE
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#undef HANDLE_VP_TO_OPC
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